8 ch countdown timer - doable in a CPLD?

Hello,

I'm new to the world of CPLDs or FPGAs so please be easy on me. We have a requirement for an 8 channel (12 channel would be better) countdown timer at 12 to 14 bit resolution with a 20MHz clock input.

All we need is to be able to load the channel's timer value via the processor's data bus and start the timers after the last channel is loaded. We need 8 (or 12) outputs that go high during the countdown and turns off when the timer times out and stays off until the next time they are loaded.

Is this possible in a relatively cheap CPLD and which "family" would be a good starting point? If this is a complicated design we would certainly entertain the possibility of farming this out.

Thanks,

Richard

Hello,

I'm new to the world of CPLDs or FPGAs so please be easy on me. We have a requirement for an 8 channel (12 channel would be better) countdown timer at 12 to 14 bit resolution with a 20MHz clock input.

All we need is to be able to load the channel's timer value via the processor's data bus and start the timers after the last channel is loaded. We need 8 (or 12) outputs that go high during the countdown and turns off when the timer times out and stays off until the next time they are loaded.

Is this possible in a relatively cheap CPLD and which "family" would be a good starting point? If this is a complicated design we would certainly entertain the possibility of farming this out.

Thanks,

Richard

Hi Richard -

[1] Suppose 12 channel x 14 bits = 164 FF. For counters. Decode logic sizing is processor dependant, but assuming "simple" synchronous IO strobe with decoded address bits for port decoding, this consumes combinational decode as opposed to FF. I would be looking at a device with maybe 200 FF. [2] 14 bit counters should clock at close 100Mhz + in a CPLD. [3] Try Xilinx 9500 series CPLD. Example, XC95288 offers 288 FF. They have families for different voltage ranges, power consumptions, but this ought to guide you to one solution. Xilinx may not be the only candidate. Lots of vendors offer free compilation tools for their smaller devices .... Xilinx is such vendor. [4] Definitely not challenging. 30 minutes to 2 hours experienced designer. Core design is simple ... but all designs have their curve balls that were not obvious up front. Try a local university ... lots of good students anxious to demonstrate their HDL skills.

-- Regards, John Retta - Colorado Based Xilinx Consultant Owner and Designer Retta Technical Consulting Inc.

email : snipped-for-privacy@rtc-inc.com web :

I'd recommend contacting your Altera rep to find out if the MaxPlus-II devices are available for you. For your application, these chips could be the cheapest way to go. Normally a CPLD in >> 128 macrocells won't be extremely inexpensive. Not bad, but not the savings you can achieve. The MaxPlus-II devices are like tiny, old-generation FPGAs with embedded flash memory giving you full functionality without external boot memories.

The no-frills architecture (who needs PLLS or RAM for your application?) fits with no-frill requirements.

If these relatively new devices are available, they may be the most cost-effective way to go.