Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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slimming down ISE install
Just installed ISE webpack 13.3 on my laptop and things are getting a bit tight space-wise - a lot of space (several gb) appears to be used by files for device families I'll never use, but removing...
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12 years ago
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Verilog module in VHDL project - ISE 13
I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff to...
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12 years ago
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Regarding FFT & IFFT CORE IN XILINX
Sir I am trying to use FFT 5.0 core in xilinx as follows for 50 hz Sin WAVE(THROUGH ADC)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p data width 8 bit 4.Scaled 5. Natural...
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12 years ago
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DEBUG a FIFO output on Virtex5 using CHIPESCOPE
Hi All, I'm a relatively newbe of FPGA development. We are working on a design involving BFSK modulator / demodulator pair. We are usign the built-in FIFO18 component of Xilinx for Virtex5. For some...
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12 years ago
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This comp.arch.fpga group is suck - I'm leaving now
Dun't know why, this group being moderated or something? But some of my posts didn't make it. I thinks others would experience the same thing. Just check usenet group statistics, these days it makes...
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12 years ago
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Xilinx platform cable crashes SL6.1 box
Has anyone else experienced systems crashes caused by the Xilinx platform cable, it's happening to me a couple of times a day. I'm using SL6.1 (RHEL 6.1 clone) and ISE 13.3. The scenario is that...
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12 years ago
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Xilinx virtex-5 pitfalls
Hello People. Thought I'd share with you, the latest harvest of pitfalls when using xilinx virtex-5 (FX) FPGAs. Pitfalls that makes the difference between a prototype and reliable product. 1. First....
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12 years ago
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Equivalence between "XtremeDSP48 slice" and "slices of programmable logic"
Hi folks! In this page ('ve found this: "Each DSP48E slice (Xilinx Virtex-5) is equivalent to over 500 slices of programmable logic, consumes 1/10th the power of an equivalent logic implementation"....
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12 years ago
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High-bandwidth Digital Content (HDCP) keys with FPGA?
Does anyone know how I could safekeep HDCP keys legally by implementing the HDCP (and HDMI/DisplayPort) engine in FPGA? (Yes, I know HDCP is cracked and that I can generate keys using the leaked...
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12 years ago
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Clock distribution for ADC and jitter
Hi everyone, I've got a question regarding clocks and jitter. Let's say I have 2 ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter crystal connected to an FPGA and then I use the FPGA...
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12 years ago
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On-chip, high-speed CAN tranceiver in NXP LPC11Cxx
Hello, Who knows if the transceiver is really on-chip or if it is two die solution in one housing? Heinz
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12 years ago
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D-Type Flip flop with negated Q in Webise for a schematic capture
Sorry for the naive question, but how do I capture a schematic with a D and J-K FF that do have negated Q? I tried to draw the schematic with WebISE 13.3 and there is not such a thing readily...
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12 years ago
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Lattice buys SiBlue for $62 million
I think this will be one of the more significant semiconductor acquisitions of the year. I've been using Lattice parts for the last few years and I plan to be using SiBlue parts this coming year. I...
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12 years ago
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Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!
HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My customer has given me the following requirements: Carrier board has 144 bidirectional...
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12 years ago
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DDR2 read interface
Hello, I have a question regarding DDR2 memory controller. In a read operation from DDR2 based on strobe, do one need to shift the strobe by 90' in order to capture the valid data, or is there any...
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12 years ago
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