Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea
The Embedded System on Chip Lab of the Hallym University seeks to recruit promising PhD and MSc research students. The selected students will conduct research in the [Processor Architecture] and [VLSI...
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12 years ago
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Using both Verilog and VHDL for Xilinx simulation
Hi, How do I setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for instance have SIMPRIM point to both the VHDL and the Verilog compiled library path, I did try using a :...
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12 years ago
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Major New Release of Public-Domain FPGA Architecture and CAD Research Software: VTR 1.0
For those interested in FPGA CAD and architecture research, we are pleased to announce the full release of the Verilog-to-Routing (VTR) project version 1.0. VTR consists of a suite of CAD tools,...
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12 years ago
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problem with Global Clock pin and normal IO pin as Clock input
hi i am trying to detect falling edge of a 200ns pulse(WriteStrobe) synchronously with this code. GlobalClk is 100MHz(10ns) oscillator clk attached to global clk pin of Xilinx Spartan 3 XC3s400-5I....
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12 years ago
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JAM Stapl player on 64 bit platform?
Hi, A few years ago I've prepared the customized version of JAM STAPL Player, well suited for operation in VME based environment with SCANSTA111 bridge (open sourced and published e.g. at It worked...
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12 years ago
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Anybody here got a Xilinx ML605?
I'm having trouble running the application described in XAPP740 (Designing high-performance video systems with the AXI interconnect). I have tried running the pre-built images, and building my own. In...
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12 years ago
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LUT6 FPGAs and Carry Logic
Hallo. Some questions about Xilinx LUT6 FPGAs (my WebPack Toolchain is a little outdated, and the newer LUT6-FPGAs don't seem to show up correctly in fpga_editor). * Is there really no carry-bypass...
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12 years ago
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MPMC simulation
Hi, I am simulating MPMC with Isim version 12.4. I have written a test bench to give inputs to microblaze instance. Here i am facing problem of MPMC simulation. The MPMC is not generating NPI output...
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12 years ago
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Dangling all pins, DIA0 through DIA31
I'm creating a dual-port ROM, both sides are the same: 7-bit address, 32-bit data. Very simple ISE 13.3 project can be downloaded from here: Implementing and Generating the bit file gives warning like...
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12 years ago
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Life after XDL
If you know and love XDL or XDLRC, and if you believe that the research community's access to these tools provides a benefit to Xilinx, this is your opportunity to speak up. The xdl tool will no...
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12 years ago
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Problem with post-route simulation
The whole ISE project (VHDL) can be found here: Besides ISE project, it also contains two print-screen GIFs, and shows @40ns : start = 1, data = AAAA at next rising CLK edge CS goes LOW then, SDI...
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12 years ago
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'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation
I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2; endmodule The input is: add1 = 2'bx0; add2 = 2'b00; The RTL simulation result is:...
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12 years ago
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Free GUI top level integration tool for Verilog and VHDL
VTC has been developed for very long time. It has been used in many projects and proven to be useful. It should have been available for you long time ago. But I have to spend many years to study laws...
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12 years ago
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Re: A smallish starter Kit for led control
I guess I did not put a question here. But you guessed correctly, a starter kit pointer or name is what I want. It seems I'll know a good starter kit, when I dont need them any more. 29.9$ is surely a...
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12 years ago
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Xilinx Artix-7 availability
did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7A8 or XC7A15 in the FTG256 Package. regards Arne
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12 years ago
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