Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ICTP Open Hardware Initiative – Invitation to part icipate in an open-survey.
Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP -...
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12 years ago
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recomendation on a processor core
hi, after few years i want to restart FPGA development once again - initially f= or personel fun, but later may move in to commercial development too. At th= e moment i am trying to find a suitable...
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12 years ago
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XSpi_Transfer within interrupt context
I'm using the standalone bsp for a ppc440 on a Virtex 5. I have a scenario where I have to read from an external chip over spi in response to a gpio interrupt. The issue I run into is that when I call...
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12 years ago
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The Xilinx Definition Language
Does anybody somewhere have a backup of this document, which was part of ISE 6.3? Regards, Jurgen
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12 years ago
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strange letter from Xilinx
In 2001 I bought a seat of Xilinx Foundation (before Ise). I did not renew the service contract because it was working fine, and then Ise and WebPack came out. I had to go to the post office to sign...
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12 years ago
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Partial reconfiguration: bus macros
Hello, I am trying to do DPR on an Atlys board, which uses Spartan-6. It seems I c= an only solve my problem if I revert to bus macros (Partitions are only sup= ported for Virtex/Kintex and you need...
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12 years ago
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Data Transfer from PC to FPGA through USB
Hallo guys, I'm pretty new to hardware programming. I'm currently working on a project and I have to create a communication channel between my PC and FPGA (Xilinx Virtex 5 model) through a USB port....
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12 years ago
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FPGAs directly plugged into CPU socket
I'm looking to purchase an FPGA that plugs directly into motherboard CPU sockets. I've only been able to find this DRC Accelium coprocessor (PDF warning: limits me to finding a motherboard with socket...
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12 years ago
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RPMs in xilinx 13.2
Hi, I am using xilinx 13.2 for synthesis and implementation of my design. I wanted to create RPMs of some small logic so that I can reuse it anywhere in my design by just instantiating. But I cannot...
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12 years ago
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Best FPGA for algorithmic acceleration
Hello, I'm looking at different options to use FPGAs as coprocessors for algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or the Altera Stratix IV (360, 530 or 820), what would be...
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12 years ago
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Watchdog reset for fpga designs
hi i 'm designing a board with fpga spartan 3(Industrial series) . while testing the board, specially when there is spike on any input pin of fpga, fpga enters unknown sate and won't do its job...
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12 years ago
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Any people having experience with HWICAP?
Dear all, As a lab project I need to check the possibilities of the HWICAP interface in the context of setting up a SoC using MicroBlaze and doing a partial reconfigure (in this case most probably...
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12 years ago
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LX9 and internal reset - Do I need one?
Hi, I am slowly implementing my morse keyer using a Avnet LX9 board. BTW, thanks all for your sugggestions, in the end I decided for this one (Gabor, you won!). I stuffed a lot of things in the...
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12 years ago
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Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
Having not done any free seminars for a while we now fixing that by running 2 sets of seminars in May and possibly into June if we add some more dates. Both sets of seminars are based on the...
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12 years ago
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Very poor Xilinx experience
I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short version: I've bought an SP605 board, it looks as though it's broken - there's no...
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12 years ago
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