Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Strange behavior with counter (decreases instead of increasing)
Hello all. I have a very strange thing happening with my FPGA. I have Xilinx Spartan-3E FPGA, that I am programming to count external pulses in 1us time bins. The way I'm doing that, is I have a pulse...
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11 years ago
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Interface Xilinx KC705 to BeagleBone?
I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex development board. This will give me much more CPU processing power than a microblaze...
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11 years ago
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FPGA basic devtool options and prices?
I know this is a complex issue and that tool providers won't talk loud about it, but Im trying to find effective tools (and their cost) without having to call the providers and having them constantly...
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11 years ago
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FPGA + HDMI 1080P
I'm looking for a FPGA board that can support HDMI/DVI 1080P in/out. I'd like to avoid building my own, I'm probably looking at a volume of 100 units. Any thoughts/suggestions? Thanks! John P
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11 years ago
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Xilinx UCF: Adding "Virtual Grounds"
Hi, Quick question. I want to connect a number of FPGA I/Os to ground without changing my VHDL i.e. via a constraint in the UCF file I have tried a number of things without success: NET GND LOC =...
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11 years ago
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Initializing inferred blockRAMs / ROMs without $readmemh (Synplify)
I've discovered that Synplify no longer requires the use of $readmemh / $re= admemb to initialize inferred blockRAMs or ROMs. I thought I'd post some e= xamples of this for my own future reference....
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11 years ago
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use differential I/O simultaneously
Hi all, Are there any method to use differential I/O simultaneously? Firstly, route in_P + in_N pad to pad connects to out_P + out_N. Secondly, route IBUFDS ( .I(in_P) .IB(in_N) .O (out_put) ); The...
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11 years ago
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What is best/good way to create a small delay with LCMXO2-1200ZE ev kit
I need a delay, lets say 10us. I could use a lot of counters to get it from clk, but there probably is a better solution already built in the chip/kit. And of course what is the signal name I can...
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11 years ago
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Completely puzzled: Strange shift register behaviour
Hi, I am not an FPGA expert although this is not my first design. The problem that I am having for two days now, is that I am observing different results when simulating a design in GHDL and in...
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11 years ago
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XAUI on V5 FX200T
I am trying to implement a 10G MAC/XAUI design on a Virtex 5 FX200T FPGA. I have tested the same design on a V5 LX100T FPGA successfully and have now generated appropriate MAC/XAUI cores for the the...
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11 years ago
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Possibility to use MGTREFCLK1P/MGTREFCLK1N as clock for user logic in Spartan 6?
Hi, Due to broken design of the FPGA board, I have the master clock available only at MGTREFCLK1P/MGTREFCLK1N pins. Is it possible to use those pins to produce clock for use logic in FPGA instead of...
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11 years ago
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RE: now what is this? iMPACT:2356 - Platform Cable USB firmware must be updated.
its been about 40 min and it is not even 1 % how did you solve your problem??? --
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11 years ago
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XC9500XL keeper ?
I just migrated a project from the XCV9500 to the XC9500XL, and am having some problems with keepers on the used inputs. Looking at Xilinx' docs on the 9500XL series, it looks like the keeper may be...
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11 years ago
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accumulator (again)
Dear All, I'm not an expert in VHDL, i'm just a curious trying to solve a research problem with an FPGA. I'm using a 32 bit accumulator in a IP, as part of a SoC project with a microblaze, implemented...
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11 years ago
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Generate a pulse with a definite width
hi is it a good practice to generate a pulse strobe in Verilog with this code? or do i need to write a fsm for such applications? BoardConfigReceivedStrobe is set elsewhere in the process. for...
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11 years ago
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