Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Altera GX45 to GX95 upgrade
Hi, We designed a board that uses an Arria II GX45 chip. We didn't initially figure to use all its resources, but the customer keeps piling on requirements and we've run out of stuff inside. The...
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11 years ago
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How do you do an incdir in Vivado
How do you set up search paths in Vivado so that it will find `includes files? XST supported incdir (in the form of the -vlgincdir switch). I haven't found an incdir in the Vivado documentation, does...
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11 years ago
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PKzip cracker
Has anyone created a PKzip password cracker from an FPGA ?? Google does not find any ...... hamilton
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11 years ago
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recruit FPGA design engineer in Scotland
The candidate needs to familiar with development of Altera FPGA and Verilog HDL language, It is better if the candidate can familiar with wireless communication and or C++. It is fix term project ,the...
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11 years ago
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"Decimals" word in binary space
Im looking for an equivalent word for "decimal" in a binary number. The "deci" says it's all about base 10 numbers, but I miss an official term for the 1/(2^n) digits. I'm using "binimals" in lack of...
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11 years ago
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My Spartan3 video
Hi, I'm not sure, if I posted it allready, but here is my video again : - Thorsten
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11 years ago
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Spartan 3AN prevent readback ?
I am trying to prevent readback of the bit file from a Spartan 3AN. I am using ise 10.1 (need to keep that for a while to support some older devices). I looked up how to do it in a Xilinx tutorial,...
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11 years ago
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xilinx fir compiler
I have used altera DSPBuilder for several multichannel multirate filter designs. I have heard that xilinx fir compiler(latest one possibly) can process multichannels even if they have different input...
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11 years ago
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spartan 6 ddr2 pinout
I've just run a DDR2 based MIG through place and route and tried the simple= st of pin swaps, which failed. The default pinout is terrible for PCB routi= ng, does anyone know whether any swapping is...
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11 years ago
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64-bit kernel mode driver for Avnet Virtex 5 LX110T PCIe development board
Hi, I have been using Avnet V5 LX110T PCIe develoment board on a Windows XP 32-bit platform with generic 32-bit device driver from Jungo. I need to migrate to a 64-bit platform as my app requires more...
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11 years ago
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how much costs the Artix 7 devices?
Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: It says "low cost", but how low is low? Is there a distributor who has stocked it or shows at least a lead time? And there is no...
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11 years ago
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3 to 1 mux with 4 bit inputs
Hi all, I'm learning Verilog. Trying to design a multiplexer: module vector_net_multiplexer_tb; reg [3:0] input1, input2, input3, sel_ip; reg [1:0] sel; initial begin $dumpfile (""); $dumpvars (1,...
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11 years ago
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manual interconnect changes
Hello, I'm looking for a way to manually change interconnect switch connections. I'm trying to simulate random bit-flips to test my solution for switch-based SEU detection. However, I'm at a loss in...
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11 years ago
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Spartan 6 IBERT confusion
If I use the core generator to generate an IBERT for a Spartan 6 and try to= implement the example design the errors I'm getting I'm not understanding.= I'm assuming I'm not understanding the back box...
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11 years ago
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MapLib:978 - LUT6 symbol error during Mapping Stage
Hi, I've recently started to use the Xilinx EDK tools to create a system in whi= ch there are two AXI masters. I made these masters and then imported them u= sing the Xilinx EDK IP tool so that they...
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11 years ago
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