According to Xilinx all blocks related to 64B/66B is impossible to use for bitrates below 10.3Gbps.
In my design I would like to use the scrambler/descrambler and the Block Sync functions of the 64B/66B encoding (not the 'coding table') at ~5Gbps. In the Rx path I would also like to use the stretch buffer to get into my system clock domain. If I have to design all the 64B/66B functions in FPGA fabric a separate clock domain is needed for each Rx path of the used MGTs, I will use 8 MGTs. The only usable part left of the MGT is the serdes function.
Is this true? Has anyone used the 64B/66B in a design for bitrates below
10.3 Gbps? What can the reason(s) be to not support sub 10.3Gbps? Looking at the block diagram, the interface signals and the attributes the MGT seems very flexible but ...