Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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fixed point fft butterfly stage testing help
I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written. module butterfly #(parameter size=16, Q=4) (input signed[size-1:0] a_real, input...
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11 years ago
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Spartan 6 MCB refresh timing
Hi there, I'm designing a memory solution with a Spartan 6 talking to 2 128MByte 16-bit-wide DDR3 RAMs. As my application is timing critical I can most probably not use auto refresh, so my question is...
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11 years ago
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modelsim SE 10.0C SystemC bug about initializing sc_signal
I am very disappointed that I get different results from the same initializing code in SC_CTOR from 6.6 and 10.0 versions of ModelsimSE. In ModelsimSE6.6 I can initialize the sc_signal vector (array)...
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11 years ago
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FPGA-Board for Ethernet
Hi, I am searching a FPGA board for a project where i have to connect an twiste d pair cable to a FPGA and send&receive packages on a pc. So it will look l ike this switch FPGA Board PC UDP will be...
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11 years ago
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fft in fpga using polar form
i understand that representing large number of twiddle factors that are req uired in a fft with large number of points is an issue when using fixed poi nt scheme. To my understanding (which could be...
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11 years ago
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Need Terasic LTM Module
Hi, I delayed too long in ordering a Terasic LTM touchscreen module and now they are listed as phased out with no substitute shown. Anyone know where I can get one? Or equivalent? Thanks, Gary
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11 years ago
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JTAG access from user design in Altera FPGAs
Hi, does somebody know, how to access the JTAG port from a user design (VHDL) in Altera FPGA (cyclone 4)? TIA Ludwig
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11 years ago
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Replacing Logic with an FPGA/CPLD in a 510K device.
Does anyone have some good links on FDA requirements for replacing TTL logic with an FPGA/CPLD ? This is for a Class 3 device. Does the FPGA/CPLD design files constitute "firmware" and needs to be...
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11 years ago
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Multiple IDELAYCTRLs in V-5: how, and why?
I'm on Virtex-5, and have a lot of IODELAYs, for fixed and variable input delays. I've read chapter 7 of the User Guide, and AR #39966, about IODELAY_GROUPs. I need to instantiate one or more...
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11 years ago
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Just gloating
I've got a VHDL design in which I use record types as a convenient way of wiring up my internal buses. This design is a single-master, multiple slave bus. The default assignment to all of the slaves...
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11 years ago
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edge matching
Hello 1. I'am a beginner in want some help. I'am trying to write code for matching rising edges of two different pulse train signa,so that AND operation can be performed b/w them . synchronization is...
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11 years ago
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Getting in to the industry
Hi, I'm new to FPGAs but would like to get into the industry. Aside from building and playing around with toy projects, what can I do to help put me ahead of the other EE graduates? What kind of...
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11 years ago
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Error while running implementation through unix command line
Hello, I am new to Xilinx and bash scripting. I am using Xilinx 13.4. I am trying to run implementation(ngdbuild, map, par etc) to create the bit file through a bash script, but I am getting an error....
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11 years ago
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How to estimate PEAK power consumption on Xilinx FPGA ?
Hi, Is there anyway to estimate "PEAK power consumption" using an Xilinx XPower analyzer ? I think the "Summar" page shows AVERAGE power consumption. Thanks, Jeong-Gun...
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11 years ago
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JTAG3-parallel cable on SPARTAN-3 digilent Starter kit
Hi all, I have been trying to make the JTAG3-parallel cable with SPI work with spartan-3 board on red-hat linux(both from digilent) The Jtag3 seems to detect the fpga and flash in chain but it does...
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11 years ago
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