Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Altera delivery
We are seeing huge leadtimes on Altera FPGAs, specifically Arria II GX65 and 95. Numbers like 20 weeks and worse. Is this specific to Altera, or to Arria parts? I wonder if all the cell phones and...
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11 years ago
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RE: Xilinx Xact software for XC2018 Logic Cell Array
My friend and I made an FPGA module that may fit your needs. It packs a Spartan-3A XC3S200A onto a breadboard-friendly 64-pin DIP package - super easy to integrate into your own project! No need to...
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11 years ago
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Re: Actel Designer: how to compile VHDL top & EDIF submodule together?
Hello Marek, Can you explain what you exactly did in your design, so you succefully can compile a VHDL with an EDN file? I have an edn top design, created by presicion, and a UART VHDL core of Actel,...
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11 years ago
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production life of Spartan3A ?
Hello, Anybody have any idea how much longer the Spartan 3A will be in production? I'm hoping a good while, yet, as it appears to be the cheapest modest-size FPGA from Xilinx right now, about $8 for...
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11 years ago
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CFP - Journal JSA (JCR-indexed journal, Elsevier) - Special Issue on: Design Space Exploration of Embedded Systems
Call for Papers - Journal of Systems Architecture (JCR-indexed journal, Elsevier) Special Issue on: Design Space Exploration of Embedded Systems --- The special issue is open to any topic related with...
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11 years ago
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Periodic reads - Xilinx Virtex6
Hello! I read that the MPMC memory controller sends automaticly (1us period) periodic read request to the DDR3 module to measure the phase detection. ( -> Disabling Periodic Reads During Writes) I...
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11 years ago
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JTAG and Altera Cyclone-IV
Hi, I would like to ask for some input. When this device is in JTAG reset state, how does it drive the outputs, hi-Z, 1'b0, 1'1b1, or unpredictable? Thx, Dtrang ---------------------------------------...
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11 years ago
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tell QuartusII to use registers and not RAM
Hi, I'm run out of M9K resources on a design while logic is less than 15% used... and I have a few components in the design with small pipelines etc that compiler infers RAM and I don't want to. What...
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11 years ago
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Serial LVDS ADC to spartan6
I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a single HDMI connector for this. The converters I'd like to...
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11 years ago
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Phase 15.18 placement optimization
I'm working on a Virtex 5 project containing a 13-stage pipeline clocked at 200 MHz. The data path gets quite wide in the latter stages; but only 11% of available slices are used; so the FPGA is...
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11 years ago
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.do files... why?
Alright, I've got to fess up. I'm lost as to the point of .do files. They seem to suffer through all of Tcl's wacky syntax, but with the added benefit of not giving you access to the standard Tcl...
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11 years ago
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CFP Special Issue on Hardware Implementation of Machine Vision Systems (Image and Video Processing)
*** Our apologies if you receive multiple copies of this CFP *** ========================= ========================= ================ EURASIP Journal on Advanced Signal Processing Special Issue on...
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11 years ago
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DIGILENT DESIGN CONTEST 2013
We proudly announce the 9th annual Digilent Design Contest Europe, organize d within the Technical University of Cluj-Napoca, România and sponsored b y Digilent! The goal of this international...
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11 years ago
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My First CPU but.. one problem
Hello to all, I completed my first CPU in VHDL, an incredibly satisfying feeling! : D I simulated successfully but I did not understand what it means to a signal colored red in ModelSim: I notice the...
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11 years ago
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ise 32b or 64b?
Hi! Using Xilinx flow (command line, ISE 13.4)... 32b version vs 64b (under Linux, 64b OS)... memory usage: || | 32b | 64b | | xst | 1614M | 2986M | | map | 1563M | 2889M | | par | 1365M | 2404M |...
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11 years ago
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