I've been trying to divide a 60Hz signal down to 1Hz and slower using an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input which seemed to remove some problems. It still has random delays in the output. Is 60Hz too slow for this device?
An RF choke sounds good, but you should have more than that.
A Schmidt trigger so it doesn't count noise that still comes through. Otherwise 60Hz counting isn't too slow, but the edge must be faster than that. If you put it through a few inverters (and make sure they don't get optimized away) that would speed up the transition.
You need a good sharp edge transition. Buffer the signal with a schmidtt-trigger, something along the lines of a 74HC14 should work. Tie the HC14's unused inputs to a single level so they don't make the unused output chatter.
I'm assuming you have already done some kind of signal conditioning on the
A 60Hz sine wave certainly is. Where does the 60Hz come from - i guess the AC mains [hopefully isolated]?
You will need a low pass filter, and a schmitt trigger, to give the fast clock edges the PLD likes. The low pass filter can be series R with shunt C, and should have a corner < 100Hz. There is a lot of glitch noise on the AC mains, and the 9572 will otherwise faithfully count those that fall inside the schmitt crossing band. The LPF removes that.
What else do you have in the pld? A "normal" clk? some extra ff's? I would set ff Q1 when 60 hz = '1' and QUAL = '0' and clear ff Q1 when 60 hz = '0' and QUAL = '1' where QUAL is ff Q1 delayed by a ms or so using the "normal" clk and some ff's. Use ff Q1 as your 60 hz global clk and you should be good to go. If you do this you can probably lose the rf choke too.
Low-pass filter followed by Schmitt trigger is the only safe bet. Here is the simplest Schmitt tigger: Inside the chip, route the incoming signal non-inverted to an other pin, as output. Run a 10 kilohm resistor from that output to the input. (Yes, I know, that forms a latch) Now drive the input from your low-impedance 60 Hz source through a 1 kilohm resistor. This gives you 10% of Vcc as hysteresis. For different values, play with the two resistor valus.
Costs one extra pin and two resistors, saves lots of headaches. Peter Alfke, Xilinx Applications
I get how the hysteresis and noise filtering works, but don't digital inputs have a minimum rise time spec that would be violated by this approach? Even with the hysteresis network the input would see a very slowly rising signal.
Could I make a low/no-precision Khz range oscillator by doing something like this involving a R-C feedback?
Yes. Where I have trialed this, it never gets parts bench testing. Poor noise rejection, and prone to cross talk effects etc - just poor design generally, and if it fails in the field, you are on your own....
Correct, it does, until the instant of switching, and then you have a race condition, where the IP stage is thinking about oscillating at some very high frequency, while you wait for what you hope is a clean regenerative edge to arrive at the feedback pin.
Only if the PLD has hysteresis, and even then, you also need to watch the Icc adder caused by the quasi-linear-input range.
I have made VCOs a la 4046 topology, using PLDS, but you need to keep the slew rate above a minimum that dictated ~10MHz a generation ago.
The CoolrunnerII and MAX II CPLDs have schmitt pin options.
For ACEX 1K, which I have the data sheet sitting here, (the PDF actually) rise time should be 40ns. Though an inverter or two it will likely be that fast.
I've been following this thread for a while and still can't figure out why Nathan really wants to use 60 Hz as a clock signal rather than using some higher frequency to sample and debounce it. I never saw a reply to Dan's post on what else is inside the CPLD that would warrant using the part in the first place. Clearly if all you had was a 4 bit count at 1 Hz, you could do the whole job in the cheapest 8-pin PIC micro (PIC12C508 comes to mind) which has an internal 4 MHz oscillator and requires almost no external parts (just decoupling caps).
So if the CPLD has something else going on, what is the rest clocked with, and if not why use a CPLD at all?
It's something I'm doing for fun. I built a circuit to run my Nixie tube clock but it used about 12 ICs. They were all counters used for either dividing or 4 bit counters for the numbers. My goal is to have the least amount of ICs/discretes and do it with a CPLD. This is my first time using programmable logic. (I have used a 68HC11 before) To save on complexity and parts, I thought I'd use the line frequency from the wall for my clock.
I had a schmitt previously hooked up to the 8VAC output from a transformer. It had issues with ground. I'll try hooking the opto-isolator output to the the schmitt and see how that goes.
At that low freq you should be able to simulate a schmidt by feeding the signal back out of an output and resistively coupling it to give a small amount of positive feedback.
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