Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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TTA-based Co-design Environment (TCE) v1.7 released
TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable...
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11 years ago
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full tcp offload solution with tcp session setup/teardown support
Hello, I am searching for a fpga accelerated ethernet card solution for facing tcp sessions before OS. The solution should complete 3 way handshake before op erating system/driver stage. This implies...
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11 years ago
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Button clock
Hi to everyone! This is my first message here so first of all thanks to everyone to let me post here! I have a homework, it consists on writing a processor and make it work in a Spartan 3. I did the...
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11 years ago
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IP core implementation of multiplier on FPGA Spartan 3e
i was tryin to implement an ip core of multiplier on fpga spartan 3e,but in the synthesysing process it is showing some error about routing problems.
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11 years ago
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Data output constraint
Hello, I asked some time ago for constraints learning materials. It is hard to learn only with reading, I think I should try it. Here comes the time when I think only that can help me. I have problem...
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11 years ago
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need help in writing VHDL code for modified booths algorithm using wallace tree
hi i want to write a vhdl code for booth modified radix4 algorithm using wallace tree(3:2) and need help in this.. please help
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11 years ago
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Combination loops and false paths
I creating an FPGA implementation of a old DEC PDP-10 (KS-10, specifically) Mainframe Computer. Why? Because I always wanted one... The KS-10 was microcoded and used 10x am2901 4-bit slices in the...
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11 years ago
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is this multicycle?
Hi all, A counter runs on system clock, counting from 0~95 in steps of 1. every 3 counts, registers for two signals are updated (data signal and write signal to ram). I first assumed both data and...
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11 years ago
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Do you have any BROKEN Xilinx Platform Cable Usb or II
Hi, I need this because of the stupid bureoacracy of my workplace. People in Turkey or USA are wanted. Thanks in advance, --enes
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11 years ago
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Quartus 12.1 Web Edition in 64-bit Linux - in System Sources and Probes do not work
Hi, I've installed the Quartus II 12.1 Web Edition for my students in 64-bit Linux machine, and I've found, that in System Sources and Probes (iSS&P) Editor does not work. Generally the program...
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11 years ago
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FPGA board with SD card slot (code test)
Hello, I'm looking for some kind person who could test my SD card controller. Board with SD card slot with 4 data pins connected is needed. I'm asking for it because I've designed my own board and I...
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11 years ago
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Lattice iCECube2 for iCE40 Devices
How many have used the iCECube2 tool? I am just getting started with it and it seems to be less than optimal. It uses Synplify Pro for synthesis. I wrote code for a simple enabled up/down counter...
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11 years ago
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Constraints learning materials
Hello, I'm new in FPGA world. I read some VHDL books and I can create not much advanced, but working projects. Most of my designs I tested on Spartan3. And the only constraints I always use are LOC to...
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11 years ago
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MIG help (Virtex-6)
Hi I have created a controller for DDR3 with the MIG. The MIG output folders are example_design and user_design. according to MIG report : " - example_design: This folder includes the design with...
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11 years ago
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Chisel as alternative HDL
Hi all, started to look into alternatives to Verilog and VHDL and stumbled over chisel from UCB: Any experiences and comment on this language? Looks like some challenge for me as it involves...
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11 years ago
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