Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FPGA Development Board with hard PowerPC
I am working on a channel emulator which is based on a FPGA development board and a custom based RF board connected to the FPGA board via daughter card connection (240 pins). I was using WARP 2 (Hard...
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10 years ago
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Low cost and/or small size CPU in an FPGA
What is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA ? Are there any 44 pin FPGAs ? hamilton
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10 years ago
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FPGA implementation of Interpolation controller for a Timing Recovery Loop
Hi All, I'm looking at FPGA implementation of Timing Recovery Loop and Interpolatio n controller. I would like to refer an exact implementation block diagram. I have refered Micheal Rice - Digital...
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10 years ago
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Modelsim ought to be cheaper
Why is Modelsim so expensive? It is a mature product and yet it segfaults on me all the time. Constantly. Often, when it ought to give me warnings or errors (such as when there is a port width...
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10 years ago
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Inferring Xilinx BlockRAM FIFO
The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t o infer them? Probably not. They're not that useful otherwise, unless you want to instantiate the primitive (not really),...
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10 years ago
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CFP - High-level Synthesis - Methodologies and Practice
========================= ========================= =============== Hindawi VLSI Design Special issue on High-level synthesis: Methodologies and Practice =========================...
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10 years ago
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FPGA board with 4 channel 500Msps ADC?
Hi, I'm looking for possibly cheap FPGA based board with 4 channel 500 Msps ADC (at least 8bit). The board should allow preprocessing of acquired data and transmission of results to the PC (via PCIe,...
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11 years ago
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Catapult C floating point exp() function?
Hello all, I was wondering if catapult C HLS has a built in exp() for floating point numbers. If yes is the generated RTL description vendor independent and the modules used sharable or open etc.?...
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11 years ago
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XILINX Artix-7
Hallo, hat jemand Erfahrungen mit der neuen 7-er Serie von XILINX, speziell mit dem Artix-7? Hat schon jemand Erfahrungen mit dem Demo-Board des Artix-7? Grüße Bodo
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11 years ago
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Programming the old Spartan S3E Sample Board
Folks, I bought a couple of these on Ebay as they were cheap but I am having fun trying to program them. The program is normally stored in a Strata Flash me mory on the board but the Digilent Adapt...
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11 years ago
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FPGA for large HDMI switch
I am working on a project that will involve a large HDMI switch - up to 16 inputs and 16 outputs. We haven't yet decided on the architecture, but one possibility is to use one or more FPGAs. The FPGAs...
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11 years ago
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ISIM issue with 'last_value attribute in functions
In the following forum thread, member Alex reports some odd behavior when using ISIM to simulate some code that is part of an FPGA emulation of an arcade game. Since the code is likely a literal...
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11 years ago
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MISC - Stack Based vs. Register Based
I have been working with stack based MISC designs in FPGAs for some years. All along I have been comparing my work to the work of others. These others were the conventional RISC type processors...
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11 years ago
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xcv800 free design tools
HI I have an old Xilinx board called "XCV800" .So my question is: What is the xilinx software version that supports the programming and the bit stream implementation of this kind-XCV800- of FPGA...
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11 years ago
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What a Xilinx fpga could do in 1988
I'm writing up a project that ran from 1988 to 1991. It involved building an ECL-based digital processor that ran at 25MHz, working into a couple of ECL SRAMs. Debugging the hardware was tedious and...
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11 years ago
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