Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Parallella-16 lowest-cost xilinx zynq kit
The crowdfunded Parallella-16 starter kit from adapteva seems to be the lowest-cost xilinx zynq starter kit at the same time. For USD 99 one gets a XC7Z010 board with 1GB DRAM, GB Ethernet, Flash,...
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10 years ago
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NiosII 8.0 make error Windows XP
I am trying to build a simple hello world example using Nios II v8.0 on a w indows Xp machine. I see the following errors: **** Build of configuration Debug for project LIDAR_NIOSII_USB2 ****make -s...
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10 years ago
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Lattice Announces EOL for XP and EC/P Product Lines
This is likely not a big deal to most, but it hurts me a lot. I have one product in production and it uses an XP device. They are only giving until November to get your last time buy orders in. I...
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10 years ago
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seperate high speed rules for HDL?
Hi everyone. I'm trying to find out if, at high speeds, it is necessary to clock every other register using every other clock transition. For instance , clocking every other register in a shift...
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10 years ago
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Instruction time (lwi) on Microblaze
Hi, I'm trying to accomodate with microblaze on a spartan starter kit 3a board and now I'm looking into measuring execution time of different things. I have a small loop that I'm analysing: while(1) {...
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10 years ago
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vtr and at40k
Hello, Has anybody ever attempted to craft a libarchfpga architecture file for the at40k FPGAs? As I understand it, verilog-to-routing is supposed to route a design on an FPGA arch, and the xml file...
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10 years ago
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serial protocol specs and verification
Hi all, I have the following specs for the physical level of a serial protocol: Isn't there a missing requirement on reset condition of the line? System clock is implicitly defined on a different...
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10 years ago
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New Relay Computer
I've made a new relay computer: check out (look for the videos on the example programs page). This one is a single board computer, like the microprocessor trainers of the 70s and 80s. A trick to keep...
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10 years ago
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FF Replication with Xilinx ISE
Hi, I have a design that needs to stall a long pipeline (with the CE input of registers). The module receiving data from this pipeline sends a busy si gnal, that within 3 clock cycles must completely...
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10 years ago
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Nios II problem with DDR core SOPC builder
Hello all: I am currently transitioning a Quartus 8.0 (subscription edition) project to Quartus 12.1 (web edition). I am facing couple of problems: 1. The NIOS II Eclipse tool does not run the code...
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10 years ago
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Verilog: "don't care" in
Hi, is there any simple way to point out impossible cases in comparison operators? For example, I have the expression result
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10 years ago
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Xilinx ISE GUI vs tcl script problem
Hello I've used tcl scripts for quite a long time now and been very happy until yesterday when suddenly the script interpreter started picking the wrong top level unit. So I have a perfectly compiling...
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10 years ago
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Metastability mitigation and I/O registers
This is a design targetted at a Microsemi ProASIC3 device, but I expect that the answer should be technology-independent. I have to input a bunch of discrete signals to send over a telemetry link....
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10 years ago
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Xilinx "Ultrascale" announcement leaves out low-cost devices
It seems that Xilinx is once again abandoning the low-cost high-volume market in pursuit of those lucrative high-end sockets. There latest announcement shows less roadmap as the devices go towards the...
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10 years ago
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Floorplanning Literature
Any good floorplanning literature (papers, books, etc.) ? I'm needing it for floorplanning FPGA architectures (Spartan 6), but any general text about the subject would be cool. I already read...
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10 years ago
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