Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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MachXO breakout board as a programmer
Hi! I'd like to use my MachXO Breakout Board as a programming device to program a custom MachXO chip on a board. Is that possible at all? I could not find anything useful in the board's user guide....
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10 years ago
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Use of hardware adders with long words to perform multiple additions in parallel
I was solving a problem, when I needed to calculate every clock a sum of multiple values encoded on a small number of bits (the latency of a few clocks is allowed). A natural solution seemed to be a...
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10 years ago
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Verilog! How to work with modules?
Hello! 1.sorry for my poor english 2.i have the following diagram to implement in verilog: http://elf.cs.pub.ro/ac/wiki/_media/teme/tema2/ I want to make an synchronous sequential circuit that...
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10 years ago
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Free VHDL Testbench library for logging/reporting and checking. A good solution - simple and powerful
If you are making VHDL testbenches you should be writing proper log message s. You should also make your result-checkers properly report mismatches and also allow positive acknowledge. Equally...
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10 years ago
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LCD test on Spartan 3E FPGA
Hi, I got a problem that I cannot understand how to display on the LCD of Sp artan 3E FPGA. Then, how to get the inputs and outputs of a 16-bit Ripple C arry Adder to show on LCD? Please any one who...
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10 years ago
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Call for Papers: IAENG International Conference on Software Engineering ICSE 2014
Call for Papers: IAENG International Conference on Software Engineering ICS E 2014 Draft Manuscript submission deadline: 8 December, 2013 Camera-Ready papers & registration deadline: 10 January, 2014...
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10 years ago
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microZed adventures
We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy and a programmer, we can now actually read and write an FPGA...
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10 years ago
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Mill: FPGA version?
I've been wondering if there could be a successful (not too large, reasonable clock frequency) soft-core FPGA version of a low end variant of the Mill. One issue with FPGAs is that only two-port...
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10 years ago
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FPGA Cryptosystem
Hello all Proposed idea from my research to date: Two FPGA encryption modules: Both will have an identical encryption algorit hm; key management something I need to research further. Bob has plain...
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10 years ago
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Cyclone V hard memory controller
Hi, I try to implement a DDR3 hard memory controller in a Cyclone v device a 5CGXFC3B6F23C7. I created an DDR3 hard memory controller IP core with the Megawizard, integrated the core in my design and...
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10 years ago
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Qsys and clock crossings
I'd love if someone could tell me if what I've found is as stupid as I think it is, or far cleverer than I am. So I'm putting together a design using Qsys on Quartus 13.0. I used the Avalon-MM Clock...
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10 years ago
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legacy Xilinx software
I've been using Ise WebPack 10.1 for some time, as it is the last version that supported the Spartan 2E chips. I don't do a lot on the 2E anymore, but there are a number of units in the field with...
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10 years ago
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Call for Papers Reminder: International MultiConference of Engineers and Computer Scientists IMECS 2014
Call for Papers Reminder: International MultiConference of Engineers and Co mputer Scientists IMECS 2014 Draft Manuscript submission deadline: 8 December, 2013 Camera-Ready papers & registration...
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10 years ago
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generating clocks
Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks of 15 0MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll core since it does not generate the exact clock. If i...
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10 years ago
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how does PC communicate with FPGA?
Hi, I am unable to understand that how a PC communicate with FPGA. I have used Xilinx software to implement codes and then connected a USB cable to Xilinx test kit that did all jobs for me. Of course...
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10 years ago
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