Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Looking for a simple SPDIF to I2S audio convertor IP.
Hello! I am looking for a simple shareware SPDIF to I2S audio convertor IP. I saw one in Opencores, but it is was actually AES/EBU->I2S IP overloaded with AES/EBU extraction options....
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10 years ago
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Altera Primitives Library
Hello, I like to be able to instantiate FPGA primitives directly in my VHDL in ord er to get fine control of a design and to get full access to the hardware f eatures of the chip. Xilinx publishes...
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10 years ago
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addsubs on FPGA
Hi, I have a query on the RTL designing for addsub based implementations. I heard that addsubs are not preferred on FPGAs as they produce worse area and timing QoR. Is it true ? Is resource sharing...
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10 years ago
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register naming
Hello, is there a special term for a register that is not required to preserve its content longer than the next clock cycle? What I'm looking for is the following construct always @(posedge clk) begin...
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10 years ago
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CFP: HEART 2014 (Highly Efficient Accelerators and Reconfigurable Technologies)
****************************************************************/ HEART2014: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 9-11 June 2014 @ Sendai Miyagi,...
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10 years ago
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Optimising pin allocation
New to FPGAs, not much understanding of what goes on inside them, and I may never get very far in that direction. I'm building an app on Cyclone II that involves some parallel 8-bit wide I/O busses...
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10 years ago
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Simple Telephone Conversation on Fpga board and SSD
Hello, ? have a code like this and i have to use SSD for outputs. module telephoneConversation(clock, reset, caller, callee, areaCode, startE nd, letter, display, leds); input clock, reset,...
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10 years ago
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Use of latches in FSMs
Hello, I have read in many places that the outputs of a finite state machine must be set to their default values in order to avoid unwanted latches. However, I have a design of an FSM in my mind in...
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10 years ago
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PPC 405 communication with custom IP ml403
Hi Everyone! I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: -- Synchronous Process --Purely Synchronous with asynchronous SET or RESET IGNITE :...
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10 years ago
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ppc405 communication with custom ip ml403
Hi Everyone! I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: -- Synchronous Process --Purely Synchronous with asynchronous SET or RESET IGNITE :...
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10 years ago
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New Cloud Based VHDL Simulator-Tarang
Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not possible in Desktop/Offline Tools. No Bulky Installations Fastest Simulation Work...
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10 years ago
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XC17V08VQ44I or XC17V16VQ44I
I am actively searching for either XC17V08VQ44I or XC17V16VQ44I 0 Xilinx co nfiguration PROMS. I have an OEM customer that needs 140 pieces for a prod uction project. If you have any excess on either...
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10 years ago
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BUFG Issue on Virtex 5 FPGA
Folks, I observe a curious problem on my FPGA Build on Virtex 5 FPGA and would lik e to understand if any of you had seen this before. As part of SoC Emulation, I have coded my FPGA RTL with a bunch...
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10 years ago
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How to feed the simulated VHDL implemented synthesizer with MIDI commands from the SMF file
Hi, One of my students is working on musical sound synthesis in FPGA. To allow her to test her solution before the design is ready to be programmed into real FPGA, I needed a solution translating the...
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10 years ago
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Implementing multiple interrupts
Hi all. Some time ago, I designed a small and simple CPU to go into a project I am sort-of working on (when can I steal the time to do so). Now, I added an interrupt mechanism to it and encountered a...
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10 years ago
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