I am using a MAX II part in a new design with 3.3V supplies.
I understand why the inputs might not be 5 volt tolerant.
Altera states that the outputs are not 5 volt tolerant when driving CMOS but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of any real benefit, however this is not my main concern.
I don't see why there would be any problem driving a CMOS input provided that the CMOS input will accept 3.3V signals as high. There certainly isn't going to be any significant current flow into the CMOS gate.
I think this situation is similiar for a number of FPGAs as well.
Could someone enlighten me as to the reasons why, instead of Altera's "because we said so"