5 V oscillator output to GCLK

Better to use a resistive divider to (a) drop the 5V to 3.3V and (b) match the impedance of the signal trace. My preference would be for series termination, i.e. place the resistive divider at the oscillator end, assuming the clk trace is a simple trace (no major stubs feeding different destinations).

If the oscillator can't drive such a low impedance, you need a higher impedance divider. Then I would place it aas close as possible to the Spartan pin.

- Brian

Do both: One resistor in series at the source, one resistor to ground at the destination. You get a transmission line that is terminated at both ends. A reflection caused by a mismatch at the destination is dampened at the source.

This provides essentially the best signal quality you can get. The only disadvantage is the reduced swing at the destination. But this is exactly what the OP wants.

Kolja Sulimma

A better solution would be to feed the clock through a 3.3V buffer that is

5V tolerant. An AHC family device would do the job I think. In fact, a 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin package.

By what measure would an IC be a "better solution" than two resistors?

KJ

I just got a 3.3V oscillator driving a 2.5V input working. The oscillator has miserable drive capability and I suspect the 5V oscillator you're using may have poor drive capability as well.

Unless you have a rare high-drive oscillator OR if you're oscillating at a leisurely rate, do like the FPGA vendor recommends: use a 100 ohm series resistor.

If you use a resistor divider, your parasitics can severely slow down your edges. Our 125 MHz oscillator looked almost like a sine wave and was reduced in amplitude to the point we were getting 25% duty cycle. Not good for our application. If it was a 20 MHz oscillator, the resitor divider would probably be fine. If we could deal with 25% duty cycle we could have probably used what was there. The series resistor just plain works. The input protection on the Spartan3 is pretty robust so you can drive the many milliamps (if you have many milliamps) into the protection diode without affecting reliability.

If I wanted to be detailed, I'd understand the drive capability, the frequency, and the parasitics involved.

- John_H

Or, think like a scope probe, and do a capacitive divider, That preserves the edges, and allows higher value resistors (so saves power) Measure the pin/pcb capacitance, and Osc output swing, and then calculate the driving capacitance, likely to be in tne 30-40pF region.

Or, add a LVC1G57/58/97/98 to your parts list, and use that.

-jg

Static drive current.

Assuming the divider is matched to the impedance of the trace, as originally suggested, the oscillator would need to source and sink around 100 mA.

You don't want slow clock transitions, and high drive impedances at the receiving end. Now, the right choice of resistors probably won't cause such trouble, but it at least needs to be considered. A long clock trace (bad idea, anyway) fed with a series resistor is essentially a lumped-constant low-pass filter. I'm not sure how fast Spartan III is, but if the Tr got slowed to tens of nS it would be really dangerous. Just add a little on-chip or on-board noise, and you have extra clock transitions. I've seen this on a 5V Spartan setup that got its clock from an LVDS receiver. Some reflections on the LVDS cable caused multiple clocks that the Spartan FFs responded to. I'm sure this would only be more sensitive on Spartan 3.

I just did a board that had a bunch of logic turned upside down (-5 V and ground) and used resistive networks with matching caps across the series resistor to keep the edges sharp. This had to be done some

70 places on the board, and there's no suitable chip for such a conversion. It worked, but had me sweating until proven.

Jon

ly

Make that 50 mA, if the series resistor is 50 Ohm, and the parallel destination termination another 50 Ohm. Peter Alfke

Oscillator outputs typically can't drive PCB trace impedance types of values (i.e. 50-100 ohm) anyway so you wouldn't terminate it with that low of a resistor value. Instead you would use something quite a bit higher so that you would get the edge quality that you need and the divider to limit the input voltage to the part.

The 5 3.3V ICs are nice when you have a bunch of signals that need translating (like a bus) but if it's just a single net (or a small handful) the resistors work nicely....of course it begs the question of why not use a

3.3V oscillator in the first place.

KJ

Any reason why you wouldn't just use an oscillator that has a 3.3V swing to begin with?

KJ

I was answering within the context of what info the original poster provided which was that he has a 5V signal going into a 3.3V tolerant input. No mention of any other similar signals that might also be problems, or that the clock is a long distance away or anything, just looking for a way to use (for some unknown reason) a 5V osc into a 3.3V tolerant part.

The same can happen with any driver. An electrically long net will need to be terminated

KJ

is

When you series-terminate the driver, and parallel-terminate the receiver, each with a resistor that equals the characteristic impedance of the clock trace, then a fast transition sees just a resistive divider, not a lumped capacitance. That's the beauty of terminated transmission lines... Peter Alfke

That's true, until it bangs into the lumped input capacitance of the FPGA. You also get a voltage-loss with this focus on transmission line matching, which might give noise margin issues, as well as Buffer Current adders, from the lower Vih.

-jg

Let's not forget: "Voltage loss" was the purpose of the whole exercise... Peter

I should have been clearer : Equal Source/Load terminations will turn the 5V swing into 2.5V Hi, on a

3.3V system. The ideal Vih is 3.3V, (lowest power, best noise immunity), so this is a lower Vih, which was the 'voltage loss' I was getting at.

-jg

So let's reduce the series resistor at the source to 25 Ohm, and keep the parallel termination at the destination at 50 Ohm. That puts 2/3 of Vcc on the cable and the FPGA input =3D 3.3 V. The 25 Ohm includes the drive impedance, which might mean no external series resistor at all... Peter

Or even better, for a little more money you could use an oscillator with differential LVDS or LVPECL output. Differential signalling would reduce jitter and EMI.

Yes, that would work, However....

# You are no longer doing strict series-impedance-match termination # One can tell you are used to high-power FPGAs ;) - as this sugestion adds a cost of 33mA in power budget (@50% clk duty cycle).

Suppose the target was a Zero power CPLD ? The whole device Icc might be 14.6mA at 200Mhz - 7.5mA @ 100MHz. [OP did not mention speed, but 5V sources are