5 input LUT in virtex

I wonder why FPGA Express can't directly infer 5 input LUT, a feature of virtex (even xc5200), even for obvious expression such as: y <= a and b and c and d and e; Would anyone tell the workaround, if any, to this problem. Thank you. Regards, Taufik Siswanto

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Taufik Siswanto
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