Hi,
How does one find the legal values where "things" can be placed? Is it me or is the Xilinx documentation distinctly lacking in explicit detail?
I have a design in which ldvs is used to output 32 data pairs, 2 clock pairs and
2 other pairs from a clock input pair at 512MHz. The input clock passes thru an IBUFDS, a BUFIO, a BUFR dividing by 4 to a BUFG which drives things in the fabric. The 512MHz and 128MHz from the BUFIO and BUFR drive OSERDES and a pair of ODDR for the clock outputs.There are no problems at the place and route stage if nothing is constrained but then the pin placements are not good for pcb layout. It bombs if I try to use a constraint in the ucf file to place even the clock input in bank 10 in an initial attempt to persuade it to place the lvds outputs in banks 6, 8 and 10.
Bank 10 is "adjacent" to banks 6 and 8, right?
The error message is that "clk128 cannot possibly be routed to component bufg_inst (placed in clock region 6) since it is too far away from source BUFR (placed in clock region 7)". I would like to LOC the BUFR and even the BUFIO but where? The relationship between banks and regions and the general lack of detail is confusing me. Maybe I need to take a break. IDELAYCTRL will also need to be placed but where? I know there are 16 of them!
Thanks, Bryan