Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: ERROR:HDLCompilers:27 -
no duplicate module..still its giving error..any one can help???plz I'm sure we could if we had access to the hdl source code. --------------------------------------- Posted through
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10 years ago
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Spartan 3 JTAG problems
Has anyone come across an issue where an XC3S200 is recognised in Impact; "Right Click to Add Device or Initialize JTAG chain", and then can't read the device ID, status or indeed do anything else....
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10 years ago
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Nexys 4 FPGA Board
Hi all I'm usinf Digilent Nexys 4 FPGA BOard and I won't to run LInux kernel on microblaze and I don't have a lot of information to complete this project . Can anyone help me (link,tutoriel, help )...
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10 years ago
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how to specify which feature for a license
Hi everyone, we have a license server that hosts both ACTEL_SUMMIT feature (1 seat) and ACTEL_VISTA one (10 seats). Is there a way in Designer to specify either from the command line or through some...
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10 years ago
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Help: Altera megafunctions, Quartus II
I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the megafunction builder to create a FIFO memory, the .v file it generated is similar to the virtual prototypes created for...
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10 years ago
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more than 58'000 false paths...
Hi everyone, I started adding false paths to my design (see this thread for a context: ) but in order to avoid funny names, I started to add wildcards. My false path constraints look like this:...
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10 years ago
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Actel Designer on multiple cores
Hi everyone, I had my vbox running with one core only (out of 4 on the host) and Designer was running extremely slow, so I thought 'what the heck' I'm not doing much with the other 3 cores on my host,...
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10 years ago
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Call for designs ("give us your timing, your synthesis/par problems, your huddled critical paths yearning to breathe free")
Learning about and working with FPGAs, many times I've wondered if there is a common pool of design knowledge and best practices that I can refer to, especially when facing a particular tough critical...
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10 years ago
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synplify_pro check constraints in batch mode
Hi everyone, how can you perform a 'check constraints' run in batch mode with synplify pro? Background: I'm trying to slowly moving my entire flow remotely and in batch mode in order to support...
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10 years ago
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[cross-post] group on systemC language
Hi everyone, does anyone out there know a group specialized on systemc? I'm interested in tlm modeling and platform virtualization. Thanks in advance, Al -- A: Because it messes up the order in which...
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10 years ago
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Re: Soft-Cores processors
Hi Makni, makni wrote: [] I'm not familiar with EDK, but MBlite has a WishBone wrapper. It shouldn't be that difficult to integrate it within your SOC. Out of curiosity, why using the Microblaze when...
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10 years ago
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on-chip bypass caps
I got a spreadsheet from Altera that lists the on-chip power supply bypass caps on an Arria II GX95 FPGA. I was kind of shocked to see 32 listed capacitors, most around 1 nf, but a Vcc_core (0.9 volt)...
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10 years ago
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static timing analysis
Hi everyone, any good reference on STA? I know roughly well the principles but I've always wanted to get a deeper understanding of this - vast - subject, especially the algorithms behind it. I often...
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10 years ago
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Tristates in synthesis
How well can the synthesis tools deal with tristates? If I use the following Verilog code for a Xilinx CPLD, with t as the top-level module, and data_io and addr_i connected to I/O ports. Will this...
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10 years ago
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Digilent Drivers stuck with Fedora 20
OK, I know Fedora 20 is not officially suported .... But, the install goes through just fine. I don't see any errors, I went through all docs, and everything looks good. Udev is running and the...
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10 years ago
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