Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Undriven outputs of a module in Quartus II Synthesis
I have a module which does not drive certain output ports for certain operation modes, and that simulates fine in Modelsim. How would Quartus II (or any other synthesis software) handle undriven...
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9 years ago
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virtex4 software reset problem.
HI I made a small amendment to a tutorial I found online "" (which worked fine), but it is not working as one could expect. Can anyone tell me why? Please see my C code area with asterisk to find the...
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9 years ago
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need coding
TITLE Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications. OUTLINE The project...
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9 years ago
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Call for Papers :: ICETC2014 :: Poland
The International Conference on Education Technologies and Computers (ICETC 2014) September 22-24, 2014 Lodz University of Technology, Lodz, Poland The conference aims to enable researchers build...
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9 years ago
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in my xps implementaion elf file is not generated only the linker script is generated
these are my errors /cygdrive/c/Xilinx/12.1/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: region ilmb_cntlr_dlmb_cntlr is full...
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9 years ago
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The USB FPGA?
I've been pondering... When it comes to attaching an FPGA to a PC, there are lots of options. First there's JTAG, then there's RS232, then there's ethernet, and PCIe. But there's an elephant in this...
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9 years ago
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Free alternatives to Xilinx iMPACT?
I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to program CPLDs. Is there a free alternative (preferably some command-line tool that works on Linux)? Philipp
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9 years ago
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Old Spartan-II demo board from Insight - seeking docs..
I have dug out an old board with Spartan-II XC2S100 chip and I could use it, if only I could get some documentation for it. It looks exactly like this: It has "Insight" and Xilinx logos on it and...
4
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9 years ago
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Lattice MICO32 won't generate?
Hi, I downloaded Lattice's MICO system for windows. It opens up Eclipse, where I can add processor and memory, make bus connections or open an example. But now I'm stuck: It won't generate. There's a...
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9 years ago
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Synthesis / PAR options mess up design functionality
Hi, I'm running into a problem with a memory controller design (mid-range FPGA, 76% utilization) and am wondering if anyone out there has seen synthesis / place-n-route options causing a design to...
3
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9 years ago
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Ethernet interfacing
Any one did ethernet interfacing in Xilinx Vertex 5.
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9 years ago
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unclear tcl error
Hi everyone, I must admit that I'm pretty new to tcl scripting so this error might be plain stupid but I've failed to understand it so far. I have a makefile (taken from the openrisc repo on and...
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9 years ago
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JTAG issues Cyclone V SoC
I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog Devices' SHARC DSPs. I am working on the JTAG connection...
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10 years ago
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Recovering verilog source file from build files.. possible?
My .v Verilog source files were in a separate folder to the IDE build directory, containing all the stuff generated in the build. Then I had a hard disk crash, and (long story) everything *except* the...
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10 years ago
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Cheap spec an using an RTL-SDR
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10 years ago
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