Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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strange effect with tristate output
I'm using a XC95144XL, two pins are an input for a 5V signal, which have pullup resistors (3k3). Setting the pins to low from my VHDL design works great. Then I thought I could set it to high, too, to...
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9 years ago
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How can Spartan-6 interface with 10/100 Mb/s Ethernet?
Hi, I read LogiCORE IP AXI Ethernet Lite MAC (v1.01.b), which says that the Ethernet interface is with 10Mb/s 100Mb/s. On its spec, I find that the maximum clock for Spartan xc6slx45t AXI4-lite 120...
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9 years ago
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Could you give me an example on synthesis techniques?
Hi, I read a paper on FPGA design. It has the following statements: "Successfully simulated programs might not work on device because synthesizer tries to optimize design and it can delete some...
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9 years ago
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floating point synthesis on Xilinx FPGAs using ISE Webpack
Hi I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE Webpack toolkit. After foolishly trying to synthesize the "real" type and then...
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9 years ago
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Professional VHDL Examples?
Over the years I have taught myself Verilog and VHDL, and although I am qui te comfortable with Verilog, I feel as though my VHDL designs are just not as tight as they should be. In pursuit of...
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9 years ago
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icse syllabus
Central books online is a online Central books , icse syllabus online is a book store which provides you icse books for every class and it is the best source for all your study needs. ">
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9 years ago
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Primitive debuggable UART interface to a Nios within a multi-Nios system
I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I also foresee that this IP will not be JTAG debuggable because the integrator will...
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9 years ago
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Know any good public FPGA projects to contribute to?
Hi all, Can you suggest any good FPGA projects I could contribute to? I have some free time and want to work on something challenging and interesting. Inste ad of starting something myself I'm...
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9 years ago
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Generating a desired synthesizable binary pulse train on FPGA using VHDL
Hello Everyone I am new to VHDL programming and FPGA. I have a Virtex - 4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will be...
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9 years ago
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CFP: EECEA2014 Malaysia
The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia Pacific University of Technology and Innovation (APU), Kuala Lumpur, Malaysia...
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9 years ago
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CFP: The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Malaysia
The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia Pacific University of Technology and Innovation (APU), Kuala Lumpur, Malaysia...
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9 years ago
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vmWare supporting Avnet Virtex-5 PCIe board
Hi, I am planning to install vmWare on one of my server machines and create virtual servers on it. I need to access a Virtex 5 PCIe board from Avnet from the virtual environment. Q1. Does vmWare...
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9 years ago
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Help with Address load logic
Hi, I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all th e data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a...
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9 years ago
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Perl + Xilinx + commandline = Module::Build::Xilinx
Hello I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. ( This is a tool that you can use to create a simple makefile like script such as done by standard perl modules....
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9 years ago
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Using FPGA as dual ported ram
To interface a fast sampling ADC to a CPU I'm considering to use a fifo or dual ported ram and a small controlling CPLD. Cypress has a nice offering of fifos and dp-rams, but looking at the prices of...
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9 years ago
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