Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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NetCPU or DotNetCPU DB200 anyone?
I have a DB200 that seems to be from NetCPU, or though the domain seems not to exist. Pretty much nothing comes out in a google search. It would be nice to know the processor (it is missing from the...
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9 years ago
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Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
Hi Guys, I was asked to prepare a presentation on the topic below for a job interview: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification Someone plz educate me. I am...
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9 years ago
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Re: Free VHDL or Verilog Simulator
Use GHDL for VHDL. I used it. It can also simulate a post NGD VHDL net-list. It supports also c interface. "...andom generation using c code and VHPI..." --------------------------------------- Posted...
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9 years ago
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Functional safety guidelines
Hello, I wonder maybe someone have automotive functional safety guidelines for VHDL and is willing to share? I think there's a package available from Altera, however they charge 10k for it telling...
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9 years ago
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xc3sprog: SPI flash access for Spartan 6 LX 25 TFQ256 (Xess Xula 2)
Hi, I wasn't able to find a bscan .bit file to program the flash on my Xula2 board so I built it myself. Link follows, includes also the .ucf file (only LOCs for the flash pins, nothing else). It...
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9 years ago
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wrong waveforms in vivado waveform viewer
Has anyone experience the Vivado waveform viewer just making up waveforms? I have a module with two different signals, lets say x and y if I go down the hierarchy and add them to the waveform view...
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9 years ago
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Bidirectional Pin FPGA (Parallel ADC)
Hey guys(and gals) FPGA convert here trying to use bidirectional pins on an Altera Board within a data acquisition project. What are the ways to implement such a design in VHDL or Verilog? Thanks! Olu
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9 years ago
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xc3sprog "instruction capture is 0x3f" (solved)
Hi, if anybody else runs into the same problem with an FPGA module: xc3sprog failed to upload the bitstream to a Spartan 6 LX45, complaining "instruction capture is 0x3f". The JTAG chain itself was...
2
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9 years ago
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calculations of logic vectors and constant
what is the prefered option of arithmetic operations using logic vectors and constant? convert logic vector to integer and do the operation or to convert the constant to logic vector? I have samples...
2
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9 years ago
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ZPU-based SoC for Numato Saturn board with DRAM
Hi, this is a "public backup" of a holiday project maybe it's of use to someone: - "medium" ZPU processor - instantiated BRAM and upload of program code via DATA2MEM. Re-compiling the C-code and...
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9 years ago
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Has anyone forked any Xilinx IP?
What is the "recommended" way to do IP forking from Xilinx's repos? Not for public distribution but to have a modified one for specific purposes. The modifications are beyond the customisations...
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9 years ago
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LVDS problem - Black magic anyone?
I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. On ly 6 wirea are used: GND + Power LVDS (with embedded clock), 720Mbps UART...
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9 years ago
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What is the content of "High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI"
Hi, I read a job post which requires: High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI I know FPGA vendors have PCIe IP interfaces. What is the job content with the above statements? It...
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9 years ago
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Basic question: sequence of execution within FPGAs
Trying to get my head around FPGAs after 40 years of 2GLs. I can't seem to find a clear exposition of the following, would appreciate if someone could confirm or clarify the following assumption: I...
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9 years ago
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multicycle path - synplify pro
Hi everyone, I'm experiencing an issue with Synplify Pro E-2010.09A-1. I have to insert some multicycle paths in order to be able to implement the design (no option to break the paths with registers...
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9 years ago
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