Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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XILINX PCIe read of slow device
What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI Express. The BAR memory map is decoded and some addresses map to fast...
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9 years ago
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Altera 100-pins chip
Hello, I'm looking for suggestions for an Altera 100-pins chip which I can use in a board like this Do you have any suggestions of chip? (in Cyclone family it would be good). Thanks in advance. Rego.
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9 years ago
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[cross-post] verification vs design
Hi everyone, I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification. If you ask the FPGA developer he'd say a factor of 2/3 has to be considered...
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9 years ago
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Fast and slow clocks
I'm wondering what the correct way to handle the following situation is. Sorry this is a bit long winded. BTW, it's not homework, all that was 40+ years ago. I have two clocks, clk which is the FPGA...
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9 years ago
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Handel-C to VHDL
When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks
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9 years ago
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Non-project mode Vivado simulation?
Is it possible to run a Vivado simulation in non-project mode? I can't seem to find any documentation on how to do it. ug835 describes which Tcl commands are used for simulation, but not which to use...
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9 years ago
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Need ideas for FYP
I am student of Bachelors and going to start my FYP in some days. I am going into the field of high computation in verilog. These are some projects which I might be doing: 1.the n-body gravitational...
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9 years ago
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ISE 14.6 and picoblaze synthesis problem (translate_on/off directives ignored ?)
Hello I am trying to implement a design containing a picoBlaze (source code I hav e already used numerous times) in a new project with ISE 14.6, and synthesi s chokes on the numerous INIT parameters...
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9 years ago
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looking for systemC/TLM 2.0 courses
Hi everyone, I apologize if this is maybe not the best audience for these kind of enquiries but I'll try anyhow. I'm looking for a good SystemC/TLM 2.0 training course which is not too basic and can...
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9 years ago
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USB PHY recommendations
I have started using the TI TUSB1210 which is a USB PHY with a ULPI interface. However, I can virtually guarantee that during enumeration, the device will lock up with DIR permanently DIR high in High...
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9 years ago
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elemapprox -- The Rosetta stone of elementary functions approximation and plotting
elemapprox is an ANSI C code, Verilog HDL and VHDL collection of modules (V erilog HDL) and packages (VHDL) that provide the capability of evaluating a nd plotting transcendental functions by...
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9 years ago
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[RFC] METATOR: A look into processor synthesis - What's next?
These last few months, I have been slowly moving back to my main interests, EDA tools (as a developer and as a user), FPGA application engineering, an d last but not least processor design. After a...
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9 years ago
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CALCULUS EARLY TRANSCENDENTAL FUNCTIONS 6TH ED BY Ron Larson, Bruce Edwards
Here are instructor's solutions manuals to the scientific textbooks in PDF format. They cover solutions to all problems. If you need any, let me know its title, edition and author. If your title is...
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9 years ago
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Some newbe questions.
Hello all! I'm new here and I don't know if it's good place for asking questions. May I count on your help? ;) I have some experience with fpga but totaly zero with high speed memory. I would like to...
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9 years ago
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opencores.org
I haven't been able to reach this site for the last couple of days. Anyone know what's going on? John Eaton --------------------------------------- Posted through
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9 years ago
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