Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Topics for Projects on FPGA+Computer Archtecture
Hi, I have to work on a project related to FPGA (Altera DEI or Altera DEII) and computer architecture. Can anyone suggest good topics that I can work on individually (say for 3-4 months). Thank you in...
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9 years ago
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data memory mapping microblaze
INFO: this very same post was posted to with no follow up over few days, that's the reason why I decided to post it here where I hope to get more feedback. Hi everyone, I'm dealing with an mb-lite...
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9 years ago
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[WTF] Hierarchical designs and ATMELs CPLD fitters
I've been playing with atmels old stuff again... I can not seem to get their fitter to accept hierarchical edif. I am using the fitters from their WinCUPL download. the commandline I am using: wine...
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9 years ago
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another MicroZed project
Another board: The microZed compute platform plugs into the middle. The application board has eight DAC channels with filters and amps, two ADC inputs, power supplies, BIST, stuff like that. We put...
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9 years ago
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Transfering image file to DDR RAM using EDK
Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further manipulation using provide different techniques to transfer...
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9 years ago
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Instantiating Components or Using Generate statements
Hi Guys, Are there any differences between instantiating components and using generate statement in hierarchical structure design?? Thanks, Abdullah --------------------------------------- Posted...
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9 years ago
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Why two hold checks done byTimeQuest
Hi, TimeQuest says it uses two hold checks per each setup check. The first hold check for previous latch edge with current launch edge and second check for current latch edge with next launch edge. It...
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9 years ago
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Vivado is intensely frustrating
So, the following ROM initialization code should be entirely synthesizable. Not so, according to the latest version of Vivado, which proudly declares "ignoring unsynthesizable construct:...
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9 years ago
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Artix-7 tools, ISE vs Vivado
Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 family? I am interested in the basic synthesis/map/routing/STA steps. Aside from possible speed increase in...
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9 years ago
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Where in ISE/Vivado are the chip specific resources listed?
Hi, I am trying to create a comparison list between various FPGAs in the Xilinx universe. The unisim library lists all primitives, but not all of the primitives listed in unisim are available in all...
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9 years ago
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Send a pulse across clocks
Hello, I want to send a pulse from one clock domain to another, knowing tha t from the time event that this pulse is generated in the source clock doma in it arrives in the first rising edge of the...
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9 years ago
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[RANT] XILINX, Are you freaking kidding me ?
So I wanted to know if it was possible to update an old embedded-developmen t kit license that's expired. There's nothing on xilinx' site as far as I c an see that allows for old licenses to be...
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9 years ago
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Altera Cyclone II
Hi, I have a Altera Cyclone II design where I am looking for a good way to make a complete reset via HDL. In Xilinx there is a STARTUP macro that can be used for reset, does the Altera also have a...
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9 years ago
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[cross-post] nand flash bad blocks management
Hi everyone, We have ~128Mbit of configuration to be stored in a Flash device and for reasons related to qualification (HiRel application) we are more inclined to the use of NAND technology instead of...
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9 years ago
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CFP (Deadline Extended): Symposium on Architectures for Networking and Communications Systems (ANCS)
Announcing a deadline extension. Please note the new deadlines below. -------------------- CALL FOR PAPERS -------------------- The 11th ACM/IEEE Symposium on Architectures for Networking and...
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9 years ago
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