Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Aurora IP 8B10B problem with TVALID
I am getting unexpected SOF(AXI_OP_TVALID) signal down as shown in the figure (find the fig in attachments). I have taken example design as a reference. In the dsign, I fixed frame size (X"07"). But...
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9 years ago
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Division by a constant
So I just had a thought. Most synthesis tools (in VHDL, and I assume in Verilog) will allow you to use the division operator to perform truncating division by a constant in synthesizable code, so long...
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9 years ago
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Call for Participation: ACM/IEEE Symposium on Architectures for Networking and Communications Systems
>>> CALL FOR PARTICIPATION -- ANCS 2015 > CONFERENCE OVERVIEW > IMPORTANT DATES > HOTEL INFORMATION > CONFERENCE PROGRAM > VISA INFORMATION
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9 years ago
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Microblaze with AXI streaming interfaces
Hello, I am trying to connect my IP to the microblaze by AXI streaming protocol. I have connected my IP to the microblaze using the AXI streaming link M0_AXIS in XPS. But it seems that the microblaze...
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9 years ago
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Question about summation function
Hello! I've using VHDL for like 2 years or even more but just today i wonde? how it works. Summation function form any package, std_arith for example operates on two arguments. But this one returns...
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9 years ago
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Graduate Research Assistantship at the Computer Systems Lab, College of Electronics and Information Engineering, Chosun University, Gwangju, Republic of Korea
Graduate Research Assistantship at the Computer Systems Lab, College of Ele ctronics and Information Engineering, Chosun University, Gwangju, Republic of Korea === We seek skillful, hard working and...
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9 years ago
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Does each core of 8-core Intel processor has an independent floating X87 unit?
Hi, Does each core of 8-core Intel processor has an independent floating X87 unit? Here are some texts from Intel latest datasheet: Intel(R) Core(tm) i7 Processor Family for LGA2011-v3 Socket...
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9 years ago
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Bad condition in wait statement, or only one clock per process.
Hi, i am working on the following code but i have error as: "Bad condition in wait statement, or only one clock per process." Code: Sensor_fusion_1_output : PROCESS VARIABLE z : vector_of_real(0 TO...
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9 years ago
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Interpret a VHDL statement within a serial to paralell port
First, thank you for taking the time to consider the questions I have not a nswered. I am working on a 32 bit serial to 32 bit parallel port which reads from an ADC. Currently looking to find a better...
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9 years ago
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Intel in Talks to buy Altera
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9 years ago
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Pengadaan Pelatihan/Training PT MMS 2015
Training Syllabus: INDUSTRIAL TOXICOLOGY & HYGIENE MONIRORING (BASIC PRINCIPLES IN OCCUPATIONAL HYGIENE) Almost Running tanggal 23 - 27 Mar 2015 TRAINING DESCRIPTION: An introductory course outlining...
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9 years ago
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Multicycle paths using clock enable (in Synplify Pro)
Hi all, I am looking for a generic set of TCL commands (for Synplify) to constrain _all_ flip-flops which are connected to the same clock enable net with the same timing constraints. This would be...
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9 years ago
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Call for Posters: ACM/IEEE Symposium on Architectures for Networking and Communications Systems
CALL FOR POSTERS The 11th ACM/IEEE Symposium on Architectures for Networking and Communications Systems ANCS 2015 May 7-8, 2015 Oakland, CA, USA IMPORTANT DATES: Poster abstract submission deadline:...
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9 years ago
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code c of HM5883
good morning I want a code C for reading and writing of i2c for the HM5883 sensor. best regards --------------------------------------- Posted through
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9 years ago
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Lattice MachXO3L - new "F"sub-subfamily...
Lattice has shipped new version ov their Diamond tool v 3.4.1. for FPGA design. Changelog lists support for new MachXO3LF devices, which I can't find anywhere,. They did hint through some other remark...
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9 years ago
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