Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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hands on experience on SystemC
Hi everyone, I'm cross-posting here from the SystemC Accellera Forum since I believe I'm likely going to receive more feedback here than there. I've recently started to wonder what kind of project I...
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8 years ago
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Is it possible to have a parameterized verilog module name in verilog or systemverilog?
Hi, I am trying create verilog module that can support parameterized instance n ame. I understand that the signal width and other such things can be parame terized. But can we also parameterize the...
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8 years ago
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[Call For Papers]: The 18th Conference on Reconfigurable Ubiquitous Computing, RUC'2015, Szczecin, Poland, Sep. 17 - 18, 2015
The 18th Conference on Reconfigurable Ubiquitous Computing, RUC?201 5 Szczecin, Poland, Sep. 17 - 18, 2015 Conference Information The 18th Conference on Reconfigurable Ubiquitous Computing is...
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8 years ago
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ESP8266 based Xilinx Virtual Cable server?
Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specification available: and when it is included in the newer versions of Vivado suite:...
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8 years ago
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Oqpsk Demod
Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the difference between qpsk and oqpsk is only the delay of one bit period in q channel....
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8 years ago
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IIR filter bus width
Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it should be more reliable on fixed point designs, as mine is. My input signal is...
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8 years ago
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Clock triggered FSM
Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter...
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8 years ago
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16->5 "Sort"
I'm trying to design a circuit (Virtex-7) which you might call either a pri ority encoder or a sorter. This is what it should do: Given a 16-bit vector with 5 bits set, create a list of 5 4-bit...
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8 years ago
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ZYNQ temperature
Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin...
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8 years ago
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Spartan-3 stater kit
Dear all, I'm really not a specialist in FPGA :-) For several years now I have a microbalze SoC running on a Digilent Spartan -3 Starter Kit Board with a XC3S200 FPGA. The board acts as the digital...
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8 years ago
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Interested in VHDL and FPGA Development?
Check out my course! Lifetime and Unlimited Access!
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8 years ago
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Xilinx Aurora link splitter
Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devices A and B connected using Aurora link (single lane, full duplex) over SFP +...
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9 years ago
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Directly connect two XAUI ports inside FPGA
Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6. Therefor we did instantiate two XAUI-cores and connected...
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9 years ago
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Choosing the right FPGA board
Hello! I have several years of experience in programming, and I'd like to move on to FPGAs to enjoy more fun. As I have a limited budget for my playing with electronics, I'd like to choose the most...
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9 years ago
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does anybody use systemc in FPGA flow?
Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of c++...
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9 years ago
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