Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Question about partial multiplication result in transposed FIR filter
Hi, When I read a tutorial on FIR implementation on FPGA, I am not clear about "partial results can be used for many multiplications (regardless of symmetry)" That slide may be based on multiplier...
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8 years ago
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What equivalent attribute in Xilinx IDE
Hi, I see an example on Xilinx FPGA with tool Synplify-Pro: attribute syn_multstyle : string; attribute syn_multstyle of MULT : signal is "logic"; I only have Xilinx IDE. How can I get the above...
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8 years ago
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Can anybody knowledgeable on DisplayPort help me?
Hi, My DisplayPort project has hit a speed bump - so close yet so far! Is there anybody who knows DP and can can help me review things and bet me back on track? The AUX channel is up and running, EDID...
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8 years ago
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I am getting errors when i run a systemC Code in edaplayground
Hi, I am getting below errors when i use systemc in edaplayground error: 'sc_sgnal' was not declared in this scope. I have added systemC2.3 library aswell. using C++ Copiler. Please help me Thanks...
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8 years ago
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low-level vs. high-level
Hi, I use graphical high-level tools to design DSP stuff and generate RTL for it. It works for me, but I started to suspect that it is more efficient to write RTL in HDL languages instead. Is there...
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8 years ago
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How to understand obfuscated IP codes?
Hi, Good day to all. If suppose i received a HDL code for FPGA related design and it is obfuscated, how to understand it??? Is there any systematic procedure to perform it?? Thank you in advance....
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8 years ago
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[JOB POSTING] Full-time FPGA/Hardware Engineer
kvm-tec electronic is a small company based in Austria. We are currently looking for another full-time engineer with FPGA experience. Further details are available on our website:
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8 years ago
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Why is this group so quiet?
I was just wondering... why is this group so quiet? With lots of interesting news like: Microsoft Extends FPGA Reach From Bing To Deep Learning - China's FPGA Company - AMD patent filing hints at FPGA...
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8 years ago
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Re: Q: CPLD input mux structure
Their .jed files have comments... In this case I know which is which. guessing the and-matrix assignment is trivial(done from the input equations). The meaning of the MC fuses can be found by...
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8 years ago
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Strange way to route design.
Hello, colleagues. I'm fixing issues of the design with many clocks and its interaction on Art ix7 FPGA. In order to move data from one clock domain to another I'm using double-port distributed memory...
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8 years ago
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Picking the best synthesis result before implementation
Out of curiosity, I wrote a script to explore with different options in the Vivado software (2014.4), especially on the synthesis options under SYNTH_ DESIGN, like FSM_extraction, MAX_BRAM etc. The...
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8 years ago
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fifo or sdram bug?
In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by application software. All looks ok except that some units in the field show occasional...
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8 years ago
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FPGA board to interface with ADC (>10 GHz) and generate 5Gbps PRBS
Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to find a high speed ADC and a supporting FPGA evaluation board. Does anyone know/...
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8 years ago
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Finally! A Completely Open Complete FPGA Toolchain
I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the compiler, but the entire bitstream generation! Several...
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8 years ago
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Free Lattice FPGA
I'm turning out a cupboard and have found 10 off Lattice LFECP10E-4FN256C - still sealed in dry packs. Location SW Scotland - seems a shame to bin them - I'll try to give them away at the Wuthering...
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8 years ago
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