This application I am looking at requires 17 tera bytes of multiplication per second. Which in an FPGA means 40K FPGAs. What I want to know is how many 32x32 Mults can you fit into an ASIC today Standard Cell or Custom ASIC. Also what kind of speeds can I get.
With a 90nm process you can get quite a few in a standard cell ASIC. But without further explanation, I would say that speed per multiplier will be dreadfull: you won't be able to get that much data on and off a single chip (I/O limitations). So you may stick to an FPGA as well (saves you time and risk, read on).
As for your FPGA count: you need 3 DSP48 blocks on a Xilinx device or 1
32x32 multiplier on an Altera device. The DSP48s go up to 550MHz, for the Altera part, I don't know.
But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are more than 100 of these in the larger V5 SX(T) devices (too lasy to look up the exact number), you will end up with quite a bit less than 1000 FPGAs.
Still, you need to look at your I/O, power, algorithm, costs, etc. to get the whole picture.
But not totally outrageous. I've recently completed a beamforming antenna design for installation in an aircraft that uses one Virtex
4SX55 for each antenna element. There are 240 antenna elements, thus
240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the FPGA is a 10 channel tuner, downconverter, and beam steering.
Slightly off-topic: Here is a civilian research application at CERN, where 120 Virtex 4FX devices "digest" and pre-process a thousand data streams of 2.5 Gbps each. I was peripherally involved, and I helped write the press release...
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I even got to walk around in the tunnel. Peter Alfke, Xilinx
So that's why Volker Lindenstruth is hosting the FPL this year. I worked on something like the predecessor of that beast in 1995. Processing 100.000 data streams at 10MHz.
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