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32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)

Hi all, I wanted to use a 32/16 divider circuit in one of my designs. I found Synopsys designware provides Pipelined dividers and decided to use it. I synthesised DW-divider and found a 3-stage pipeline required to meet my timing requirement of 20MHz(50ns) in TSMC .13u technology.

Since I wanted to FPGA prototyping for my asic, I thought of using Core generator divider while synthesising for Xilnx FPGA..

Now the Interesting fact I found is, a 32/16 divider from Xlinx core genrator can be synthesised(using XST synthesis)to 150Mhz easily for a Virtex-2 (Xc2v2000)FPGA with just one stage pipeline..

At the same time DC-ultra 2004.06-1 is struggling with Designware foundation divider for meeting a timing of 20MHz with 3 stage pipeline....

I am confused.......... I always thought ASIC synthesis gives more frequency for an RTL code...

What I can assume is SYNOPSYS Designware divider is a very bad implementation of divider...

Any comments/Clues are welcome..

Thanks Deepu John

Reply to
john.deepu
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Forgot to mention that, I use Xlinix ISE version 7.1i for FPGA synthesis...

Reply to
john.deepu

I would imagine that the Xilinx core takes multiple cycles to perform the divide (and thus is not pipelined), whereas with the Synopsys divider, you can probably start one divide per cycle, each having a latency of 3 cycles. Don't know though, never used them.

Cheers, Jon

Reply to
Jon Beniston

Did you use the "Pipelined divider" with a setting of 1 result every clock? Every 8 clocks? I saw two versions of Pilelined Divider for the Core Generator when I did a quick search on the Xilinx website. There should be full data sheets there for referencing details.

FPGAs do a decent job with carry chains. Since that structure is used often enough, it's pretty decent in speed. A test I ran a while back for my own implementation suggested I could get a 16/16 divider running with about 80 ns in one clock cycle without any constraints in a Spartan-2E device if I recall correctly. A faster speed grade Virtex-2 may perform much better.

You *are* dividing by a variable, not a constant, right?

snipped-for-privacy@gmail.com wrote:

Reply to
John_H

Hi John,

Not true, I'm afraid. The Coregen pipelined divider is really, really pipelined. The pipeline depth (i.e. latency) of a divide will always be at least one clock cycle per bit of dividend width (in your case, 32 clock cycles). The field called "Clocks per division" is actually not very well named; it is really the "initiation interval".

So, if you generate a 32/16 divider with Clocks per division set to '1', and it runs at 150MHz, then you'll be able to do one instruction every clock (6.66ns), but each one will take, say, 34 clock cycles (~226ns) to complete.

If you generate the same divider but with CPD set to '8', it will most likely run at a similar speed and the latency will be about the same (~226ns). However, you can now kick off only one division every eight cycles (53ns). (The circuit will be considerably smaller than the first example.) This compares favourably with your Synopsis example, which would appear to take 50ns*3 = 150ns to do a divide (about 33% less than the Coregen one), and does one division every 50ns (about the same as the coregen one). So, Synopsis' divider is not rubbish, but it's nothing to shout about in performance terms.

The Coregen divider doesn't currently allow you to vary the pipeline depth manually (to get your 20MHz implementation, for example, by pulling out a load of registers).However, you can - with care - run the divider on a faster clock than the surrounding logic and rate match the two.

Hope this helps,

-Ben-

Reply to
Ben Jones
  1. I don't believe it can run 150MH without pipelines within the FPGA.
  2. There are some hardcore of multipliers in the FPGA and it is used to do divide by multiplications.
  3. Please post futher information about it.
  4. For pipeline divide algorithm, every clock may permit to feed data with several clocks of delays to get the result.

Weng

Reply to
Weng Tianxiang

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