Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Xilinx ISE Webpack 9.1 RTL schematic viewer problem
Hello, I have a problem with the latest Xilinx ISE webpack software (9.1, service pack 2). Nice thing is that the design (24bit CORDIC rotator written in VHDL) seems to run faster (181MHz) compared to...
 
Bypass caps, X2Y and 'puddles'.
Hey Guys, It's a been a while since we had a bypass capacitor religious war, so I thought I'd stir things up a bit! Seriously, I've been reading about X2Y capacitors, and a search of the newsgroup...
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XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"
I created a peripheral named o2p, it is a bridge to communicate the PLB Bus with a On Chip Bus(developed in my company). Using the BFM simulation, I was able to see that it works, afterthat I imported...
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google tech talks : "General Purpose, Low Power Supercomputing Using Reconfiguration"
FYI :
 
what about dma scatter /gather support in xilinx edk ipif ?
I have a project that need dma support and after I read some document and code in Xilinx EDK, I'm confused by dma support of ipif core, anyone had use it and give some suggestion ? Or Xilinx can say...
 
Regional Clock Network and Large Designs
Hello, I'm getting usual results from my BUFR network in Timing Analyzer: -------------------------------------------------------------------------------- Hold Violations: TS_adc1_dclk_p = PERIOD...
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Where can i get free CAN VHDL core
Hi, I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, and the link in opencores site for VHDL CAN core is going to some odd page. can you please guide me on...
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what does a 'blank check' do exactly
on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding information on this. Using Impact. thanks!
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Altera Byte Blaster Cable on Linux
I'm trying to use the Altera USB Byte Blaster Cable on Linux (Scientific Linux 4.4, i.e. RHEL 4). The Programmer application sees the cable, however it says there are insufficient privileges on the...
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Xilinx USB flatform cable length mistery ?
I've just ordered couple of these cables. To make them works with my JTAG connector, I built a little 10 inches thong adapter, one end connects to the existing Xilinx 2.5 mm ribbon connector, the...
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Can write, can't read with OPB_SPI 1.00e
Hello, I have a ComBlock 1200 ( FPGA board with a Analog Devices AD9860 MxFE interface. I'm trying to get the SPI interface up and running to configure it. Right now, I can write to any register. I've...
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SCons build tool as an alternative to makefiles
Hello, I have been using batch files to handle the build process with a Xilinx flow for a while. Now I want to move to a more sophisticated approach to handle dependencies better. I don't really want...
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Virtex 4 FX Sonet Alignment
Is there anybody in this group who has experience with V4FX MGT Sonet Alignment? The documentation is rather short on details. The interaction of the two alignment stages is not clear to me at all....
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PCI-E TS1s
I'm writing the initial state machine for a PCI-Express card and am stuck at the very first hurdle. I'm using a Philips PX1011 PHY and I'm able detect the receiver on the motherboard. I then send it...
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How to implement pipeline in this case?
Hello. To improve the speed, I want to implement pipeline.But variables make me sad... For example -- input: IN1,IN2 , output:OUT signal A,B,C; process(clk) variable V_1,V_2,V_3; begin V_1 := IN1 A
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