Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Nios II Multiprocessor Collection run in command line
Hi All, is there any chance to run Nios II Multiprocessor Collection in command line? I have the system with 2 cpus. I've tried to run the programs separately, but in that case mutex doesn't work...
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17 years ago
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LCD code
hey guys i want a vhdl code for lcd ( 2 lines lcd ) please i want ur help !!!! thnx
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17 years ago
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is bluespec pupolar in industry?
is bluespec pupolar in industry? is it worth learning? CMOS
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17 years ago
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Ideas for Masters Project.
Hello Everybody, I am looking for some interesting project ideas for a Masters Project. An idea/project that can be implemented on a Xilinx/Altera board and can be "seen" working. I would appreciate...
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17 years ago
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Integrate custom cores within Core Generator
Is there a way to integrate custom cores into Core Generator. i.e develop the GUI etc etc??? Best Regards Mehdi
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17 years ago
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Large power planes vs. power islands vs. slits for decoupling
I know the decoupling topic is a recurrent one but when I looked at the following page, mentioned in another thread, I noticed that they have put slits in the power plane around the FPGA: Is this a...
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17 years ago
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Call for papers on Hardware Architectures for Genetic, Neural and Fuzzy Systems
7th. International Conference on Intelligent System Design and Applications 2007, 22-24 October, Rio de Janeiro, Brazil Workshop on Hardware Architectures for Genetic, Neural and Fuzzy Systems Genetic...
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17 years ago
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EDK 8.1i : add port for component
Hi, I am using EDK 8.1i. I am trying add a port into a component. I know how to do it on EDK 6.3i but I don't know how to do it on EDK 8.1i. Exactly is add the port OPB_CLK on the OPB_GPIO. Thank you...
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17 years ago
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regarding power and timing
I have some doubts 1)consider FPGA cyclone device with I/O voltage 3.3 V, core Voltage 1.5 V,. output current set to 24mA or 4 mA I/O standard set to LVTTL or SSTL-3 or etc The operating frequency of...
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17 years ago
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CUDD
Hi all I am working on partial reconfiguration and I need to use the cudd package for the programming part of it. I am trying to permute a function for various input orders. by using the...
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17 years ago
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Boot uClinux from RAM without flash
i. I'm trying to to put uClinux on my Spartan 3 Starter Board (it hasn't flash memory and it has only 1MB RAM). Finally I've made an uClinux < 1MB (986 KB :-P ). Now I've downloaded Microblaze on SP3...
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17 years ago
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Multiplication operation
Hi every body , i hope that you can help me , i want to do this operation: s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1 when i check the syntax , i have these errors ERROR:HDLParsers:808 -...
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17 years ago
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V.34 Modem IP core
any IP vendor out there who supply hard/soft core for V.34 Modem?
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17 years ago
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New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
I am using these programs in my digital class but do not know how to link modelsim to ISE. In our school lab, after I make my schematic, I can run model sim to simulate it from inside ISE. Does...
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17 years ago
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DRP of the Virtex 5 PLL
Hi every one, I see the Virtex 5 DLL has a DRP port however I can't find the register description to change it's configuration dynamically. For the virtex 4 that was in the "configuration guide", but...
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17 years ago
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