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3 devices on the same external bus

Hi everyone. I am designing a new board with FPGA. I have man memory devices but 3 of them (sram, flash and RTclk) will b connected to the same bus. The fact is that RTclk has 5 bits addres bus and 8 bits data bus. I would like to be sure of not having Fanou problems (in just 10 lines of bus). I think I have to check inpu capacitance of the memory devices and output capacitance of FPGA an viceversa to apply the following formula toh= (MCi+Co)*K, with depending on Roh. Could you explain how to get Roh and toh. I woul like to work with 65MHz, probably 100MHz. Thank you for any hel

Reply to
calaf
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Much depends on the drive that can be provided by the FPGA, so I would need to know the specific device.

The effective output resistance depends on the driver characteristics.

Note that at those frequencies, terminating the lines is not optional with a distributed bus, and impedance controlled address / data / control would be an exceedingly good idea.

Cheers

PeteS

Reply to
PeteS

I will use the Spartan-3 FG456 package, 3.3V. I thought on 33CMO drivers as the most probable, and I will test the current of th drivers on the board. I haven't thought on termination because I hav experience with buses loading on SRAM and Flash, running at 75MH without problems (without terminations).The problem is that now have three In any case, if I have to consider bus terminations, should I confor with termination on the FPGA side (the internals) or shoud I reserv space on the pcb for terminations on the memory side? And which typ of terminations should I tconsider in both side Thank you for any feedback Regard

Reply to
calaf

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