Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
ISE synthesis works, XPS does not resolve symbol?
Hi all, I have a peripheral written in verlog, this is getting synthesized by ISE but then when I generate netlist using XPS it fails to resolve a function symbol. Could someone please explain what...
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Estimating number of FPGAs needed for an application
Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to solve a problem that ideally I was not targeted to. The issue is this: I have to...
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Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
Hi, this is the first time I work with a FPGA with a processor embeded. The FPGA is Xilinx Virtex II Pro, and the board belongs to Sundance. They say that FPGA has a Embeded Processor (POWERPC) and...
 
EDK & custom board definitions
Hi All, In the process of creating a custom board definition file for a new board I've developed I've discovered a few things about the naming and location of the .kbd files. Here's the file location:...
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Dual edge detection
Hi newsgroup, As shown in the VHDL code I am feeding two flip flop chains with the same input. The chains use complementary clocks (200Mhz). In the process "rise_fall" I do some combinational logic to...
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Need help bringing up PCIe at the physical layer.
Gentlemen, Sorry if this is the wrong newsgroup for this. If someone can suggest a more appropriate forum, I'd be quite grateful. I'm looking for some help bringing up our first PCIe product. We're...
 
Comunicate FPGA to Ethernet
Hi people, In last my design, I made a fpga board using IC xc3s400. Now i would like to modify it some following things. I want to add a part into Fpga board. I want to use a chip W5100 to comunicated...
 
Xilinx: Case Statements
Xilinx has the ridiculous peculiarity of requiring sized cases in a case statement. I allow users of my module to set parameters that are used to calculate other local parameters, and those local...
 
Heritage Data books!
hi, Pile of data books in search of a good home... I have a collection of perhaps 80 or 100 data books for various logic, CPU and DSP devices and device families, mostly dating from around 1988-1994...
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Design report does not show BRAM usage
Hi all, I have created a peripheral and attached it to the OPB bus. This peripheral is composed of a controller and also BRAM block directly attached to it. There is no bus between the controller and...
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Are FPGAs go enough for clock dstribution
Hi, I have a PCB design with a FPGA and other devices that require a clock input. Is it a good idea to first feed a single clock into the FPGA and then through the FPGA distribute this clock to the...
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ddr sdram controller
How can I get a ddr sdram controller for the MT46V16M16TG -75 micron chip. I want a controller without the plb or opb interface. I tried open but it says that the repository is empty with no files...
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Addressing scheme in Block RAM
Hi People, I have generated a duap port RAM using a Xilinx Core generator . Port A is 32 x 32 and Port B is 8 x 128 The 32 bit port , Port A , is interpreting the addresses in the row order 00 01 02 ....
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Any Western NC VHDL Designers?
Is there anyone on this list looking for side work who lives in Western NC or possibly Eastern TN, North Western SC? Please enquirer directly to Rick at ashevillecommunity dot org. Include resume' and...
 
XST 9.1 hates VHDL character types
Under ISE 7.1, I did a simple UART module that has a "terminating character" generic, which is of type character. (When the receiver sees that terminating character, it asserts a "got terminator"...
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