Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Xilinx ISE support for dual/quad core CPUs?
Hi, I'm about to buy a new workstation for FPGA development and I'm hesitating between a Core 2 Extreme @ 2.93 GHz (X6800) and the new quad-core @ 2.66 GHz (QX6700). The price difference is 100$. Does...
16
|
17 years ago
|
16 | |
|
|
Virtex5 LXT and synthesis..
Folks, I need to do a trial synthesis to see if one of our ASIC design module will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify Premiere the front end synthesis tool to use for...
4
|
17 years ago
|
4 | |
|
|
Xilinx Synthesis Attribute usage
Xilinx gurus out there, I have a very very simple design with a 24 bit counter, and I am using bit 24 in an always block like this always @(posedge cnt[23]) Xilinx is telling me that it didnt...
6
|
17 years ago
|
6 | |
|
|
XILINX ISE: How to define a Internal clock and use it in OFFSET command?
Hi, I have a input clock "i_clk_main", in my VHDL code, i divide this clk with factor 2, that means "clk_int" has the half frequenz as "i_clk_main", and i use "clk_int" to clock the output register....
1
|
17 years ago
|
1 | |
|
|
chipscope
Hi, i have used a parallel cable to download bitfile into my Virtex 4 FPGA. But when open Chipscope with this cable, the computer said it can't found the cable. Do anybody know how to solve this?...
1
|
17 years ago
|
1 | |
|
|
init of FPGA's Block-RAMs.
Bonjour, My name is Julien Lochen, I work as FPGA Design Engineer in France. My question is about the init of FPGA's RAMs. In my design, some data are stored in a block-RAM. I need to init each byte...
2
|
17 years ago
|
2 | |
|
|
How to generate sgmii interface?
I want to generate sgmii interface with coregen. I choose this IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i generate, I never find sgmii interface except sgmii_clk signal. So i want to ask where...
2
|
17 years ago
|
2 | |
|
|
old Quartus project files
I have to work again on an old project started 2004 with Quartus v3.0. Now I'm working with the actual v6.1. There are a lot of files in the project-directory :-((( therefore I want to clean up now....
1
|
17 years ago
|
1 | |
|
|
Problem with XESS XSA 3S1000!
I have created a simple project using Microblaze v4.0a and I use XESS XSA 3S1000,XStend v3.0 board. The project only had a seven segment LED pripherial (I used GPIO IP). The EDK8.1i software worked...
—
|
17 years ago
|
— | |
|
|
How to use the DDR SDRAM instead of Block RAM?
Hi, I have a design that is implemented on the Virtex4 and it consumes 69 FIFO16/RAMB16s. I hope to be able to implement it on a Spartan 3E evaluation board but clearly, it is not enough as the 3E...
10
|
17 years ago
|
10 | |
|
|
DCM Autoconfiguration??
I have ported a project that was developed on an ML401 Virtex4 board over to an Avnet Virtex4 PCI-E board. The ML401 uses a V4LX25 and the Avnet board uses a V4FX60. The only changes I made to the...
4
|
17 years ago
|
4 | |
|
|
XIlinx 9.2 'partition' mode problem - s/w dies....
I've tired using the Xilinx 'partition' feature several times now with very mixed/negative results. I tried partions again today with the 9.1.2 s/w and it dies with an unhelpful message:...
1
|
17 years ago
|
1 | |
|
|
ChipScope problem: "Waiting for core to be armed".
Hi, All The ChipScope gave me the message "Waiting for core to be armed" while the program can run on the board at the same time. I have a small test project which includes a MicroBlaze with a DCM, a...
7
|
17 years ago
|
7 | |
|
|
Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)
Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: * Achieving Unity Gain in IFFT+FFT Pair Using Block Floating Point Arithmetic * Fast Fourier Transform (FFT)...
—
|
17 years ago
|
— | |
|
|
Fpga sdr boards / kits
Need to find a decent fpga sdr board or kit - preferably xilinx. Trying to buy a premade kit rather than assembling our own (if possible). We have had a look at the lyrtech sdr boards and these are a...
—
|
17 years ago
|
— |