Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Where is MIG 1.7???
MIG 1.7 is already cited in the new versions of DDR2 SDRAM related application notes. There are also a few answer records about it. But there is no dowload link on Xilinx's site :(( Mehdi
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17 years ago
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FPGA board with multiple Ethernet connections (Gigabit Ethernet)
Hi, I am searching for an FPGA board having multiple gigabit ethernet connectivity support on it. To be more precise, I need to have multiple RJ45 connectors and associated logic (PHY) on the FPGA...
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17 years ago
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Post PAR simulation for RAM Block implementations
Hello Sir, I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the example "Dual Port Block RAM v6.1" at I generated an empty test bench for this...
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17 years ago
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No results show up after "dow" and "con" in hypertrm
Hi, all I am a student in Beihang University in Beijing, I just started to learn to build a system uClinux on Microblaze. I m reading a document named uClinux_ready_Microblaze_design_1_05_a. I met a...
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17 years ago
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Spartan 3E Not enough block ram.
I trying to port a design (video scaler) from Virtex 4 to Spartan 3E. Currently having trouble with not enough block rams. My reference (top) design uses only 15 Block Rams, but after wrapping a...
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17 years ago
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A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
Hi Lewis, I have a suggestion on VHDL function interface. Here is a point: ('-' is used to simplify the 'downto') R(63-0)
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17 years ago
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RISC implementation questions
Hi there I have some general question for implementing a general RISC architecture. I have coded so far the fetch, decode, execute and writeback stage. 1) Next step is to implement forwarding. Do I...
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17 years ago
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Minimal pins for JTAG configuration
Hi, I built a PCB with a spartan3-xc3s400 TQ144 and tried configuring it with the simple JTAG parallal cabel III from xilinx ( but ISE9.1 couldn't identify the FPGA. Since I soldered the FPGA myself,...
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17 years ago
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how to read a sequence of video
hi , please i want some informations about reading videos using VHDL : how to input videos then to treat it? please i want informations about automatic way and manual way please and thank you
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17 years ago
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Quartus warning messages reagarding timming and latchs
Dear users Thank you for your reply. I found that my problem lies in the state machine it self, so i basically removed the RAM from my project and ran the synatizer using quartus. The warning message...
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17 years ago
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Delta Sigma A/D's integrated in FPGA's
Why don't you FPGA guys put delta sigma A/D's in future devices ? The good thing about a delta sigma A/D is the resolution/bandwidth tradeoff selected by the digital post-filter. And if you already...
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17 years ago
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Small memories in Cyclone
Hi I am about to start on a design that will need a number of smallish memories. i.e. 8 deep x 16 wide shift registers, small FIFOs etc. I am looking at the Spartan 3E and Cyclone II/III. The...
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17 years ago
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Where is Open Source for FPGA development?
Many engineers today have Linux on Desktop as main-OS. Many engineers today use Open Source products because of their quality, stability, and configurability. Today I see no alternative to use Xilinx...
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17 years ago
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help needed
Dear Sir I am using Quartus by ALtera, i have made my design using VHDL and have ran it on model sim, the basic design use a state machine that depends on a clock. each state execute some vhdl code....
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17 years ago
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Tool to convert ISE project into makefile? (for Linux)
Hi All, I'm looking for a tool, or a method to convert the ISE project into a makefile, which I could run remotely without X connection. The only thing I've foond is: I don't now if it works with ISE...
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17 years ago
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