Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How is it possible to design a convolutional interleaver with sequential memory writes?
In my interleaver design for FPGA, I am using an external SDRAM for data storage. The clock cycles required to write a frame into the RAM and read a frame back to error correction unit ain't enough....
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17 years ago
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Compiling simulation libraries of EDK 8.1.02i under Linux
Hello everyone! I try to compile the EDK 8.1.02i simulation libraries with its wizard under Fedora Linux. My problem is that, although the compilation should take some time (almost 1 hour for P4@1GHz...
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17 years ago
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LC8
- Philip -- A PERSON is smart. PEOPLE are dumb, panicky, dangerous animals. (Kay)
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17 years ago
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Confuse on Spartan speed
Hello everyone, Please help. What is the maximum clock frequency that can be used on a Spartan-3 5000? I know it's a grade -4 speed but I couldn't find any documentation regarding it. -Ace-
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17 years ago
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is edk 8.1 availabe for download
hi all i am mahalingam, student from univ of south florida. i am using xilinx ise 8.1 and virtex ii pro 2vp30 board for my design. i would like to get the edk 8.1 tool and some directions in...
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17 years ago
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ANNC: Tips for FPGA Timing Closure Webcast
Lattice is holding a webcast Tomorrow Wednesday, Mar 28, "Tips for FPGA Timing Closure." The presenter will be Troy Scott, from our software marketing group. Please attend or pass along this...
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17 years ago
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What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
Hi, When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would like to know which patents filed by Xilinx to disclose the contents of Slice L. Slice M is too complex for me to fully...
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17 years ago
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longest webcase record
We did implement your suggested work-around and it works great! Much better than the Xilinx suggested workarounds. Thanks Antti! I have also be intermittently chasing this issue through Xilinx. I...
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17 years ago
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(Xilinx) OPB watchdog timer fails to release RESET
Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_timebase_wdt IP core. I'm currently using ISE/EDK 8.2.02i, and the WDT version is...
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17 years ago
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Help with Xilinx Parallel Cable IV.
I've just started a new FPGA project, and am having trouble getting the parallel cable IV to work at speed. I'm using a Win XP computer that's new since the last project, and I removed the combination...
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17 years ago
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Lattice "Open IP" license is GPL-compatible?
I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-quality tiny-fsm like picoblaze or the lattice semi micro8. However, I'm worried about...
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17 years ago
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Re: EDK : Import Custom Peripheral
Figured it out on my own... EDK doesn't happily mix languages.. remade the top peripheral wrapper in VHDL instead of verilog and it worked right away... GREAT TOOLS!!!
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17 years ago
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PCI-Express drivers with Xilinx FPGA?
Hi guys: First of all, forgive me for being a dumb mechanical engineer...FPGA's are new to me. I'm programming a Xilinx Spartan-3 FPGA development kit. I'm doing pretty well so far. I've gotten my...
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17 years ago
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CycloneII altlvds_rx
Hello, I am using the altlvds_rx core of altera to make a video deserializer in an FPGA. I have implemented the design and it is now running on my board. However, it looks like I have a timing...
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17 years ago
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Open-source CPU-core for standard-cell ASIC?
Forgive me if this topic has been beaten to death. Are there any *production-quality* open-source embedded CPU cores, that are suitable for a standard-cell (0.18u) ASIC implementation? I see lots of...
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17 years ago
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