Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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virtex 4vfx12 evaluation kit schematics
hi, can any please tell me where i can get virtex 4vfx12 evaluation kit schematics. thanks asha.
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17 years ago
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Memory Interface Recommendation for ML410 Design
Hello, I am working on my MS Thesis which involves building a PowerPC based system on the ML410 development board from Xilinx (V4FX60 FPGA). This system will need to do some intense computation...
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17 years ago
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Transition from ASIC to FPGA
Hi All, I've been working on ASICs for quite a while and now Iam required to move to FPGA domain. I'd be glad if someone could give some suggestions on what I should know, where to start how easy or...
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17 years ago
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PCI FPGA Dev Board Suggestions
I'm looking for the perfect FPGA dev board for a project I'm contributing to. I've found one that is *almost* ideal, with the drawback being lack of support for 66 MHz PCI bus rates, and an FPGA...
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17 years ago
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suitability of systolic architecture on FPGA
Hi, I understand that because of the 2d array CLB structure of FPGA, systolic architecture can be mapped efficiently into FPGA. however, what about the high IO ports requirements. if the outputs need...
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17 years ago
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having a state machine in a datapath element a bad design practice?
hi, having a state machine in a datapath element a bad design practice? CMOS
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17 years ago
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Gray code in asynchronous FIFO design
Why do we use Gray code in asynchronous FIFO? (I am aware that only ONE bit changes in Gray code at a time, but what is the advantage of that?)
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17 years ago
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Interfacing the DAC0808 to FPGA
Hello, I m building a Function generator using an FPGA!! I m almost done wid the Coding part in VHDL. I'd just like some help regarding the interfacing of DAC0808 with the FPGA. Also how th output...
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17 years ago
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Digital Receiver chip suggestion
Hi Folks, I've been active on this forum asking questions on digital receiver. Earlier I was doing most of the work in the FPGA (thats how I architected it). Due to space constraints, this radio is...
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17 years ago
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TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
I am trying to get video through an fpga to a texas instruments TMDS transmitter chip (TFP410). I would like see video out at 1280x1024 at 60 FPS. The VESA spec calls for this to be clocked at 108...
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17 years ago
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fifo occupancy bigger than fifo size?
Note: using EDk 8.2.02 with peripheral generated with the wizard with FIFO enabled and one user interrupt that is set to the fifo_almostfull line. I'm set up to generate interrupts on the fifo almost...
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17 years ago
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high number of multipliers / low cost
Hello, I need the highest possible number of multiplication operations per second at low cost. I know that several factors affect the overall performance, but since I have no idea which FPGA chips...
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17 years ago
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Can I boot PowerPC without JTAG?
Is it possible to build an application over PowerPC and download to board without the use of JTAG?. I have a non Xilinx Board with a Virtex II Pro, and at the moment I have not Parallel Cable IV so I...
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17 years ago
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Problem with PHY clocks on Spartan 3E Starter Kit
Hi, I am designing a ethernet block using the Spartan 3E Starter Kit. The design will be using the RX and TX clock provided by the SMSC PHY on FPGA pins T7 and V3 on the Spartan 3E Starter Kit. I have...
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17 years ago
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Conceptos about VCCINT,VCCAUX,etc
Hi!, Maybe this doubt is stupid but nobody has explained it to me so could you help me? What are the functionality of the listed elements into the FPGA? Why are there several of them into the FPGA?:...
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17 years ago
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