Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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System Generator pcore I/O performance results
Hello all: I have a question regarding using SysGen to create a co-processor that's used in a microblaze design. I'm using EDK v9.1 through the base system builder wizard to create a design used on a...
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17 years ago
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Ross Freeman - inventor of the FPGA
I understand that the inventor of the FPGA was a Ross Freeman, who died aged 45, tragically just 5 years after he co-counded Xilinx. Does anyone have more details of him? Best regards.
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17 years ago
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JTAG Tap Master (was: TI Tap Controller std8980)
I am looking for a working model of std8980 (TI Tap master) or any other tap master model. The one from FMF ( does not seem to work correctly! -- Amal
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17 years ago
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website for chip designers
Website, which lots ot technical information both on front end and on backend topics with expertise level on each content published. Lot of job oppurtunities also published . i think a must to visit...
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17 years ago
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SetJmp/LongJmp for Microblaze
Does anybody use Setjmp.h for Microblaze?. I have to use this library but something is wrong, so I have decided to open smtjmp.h and I have seen that there is no definition for Microblaze. Does anyone...
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17 years ago
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Newbie with bus width mismatch problem. Quartus II
Dear Altera experts, My very first project is a PWM in Quartus II 7.0. I've drawn up a block diagram with a 17 bit lpm_counter going into a 5 bit lpm_compare. All I want is the top five bits of the...
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17 years ago
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VIrtex-4 FIFO16
Hi everybody, In the new version (2.1) of the Virtex-4 User Guide (ug070), in the FIFO chapter is described the synchronous clock work-around (page 161) to solve the FIFO bug. At the end of the...
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17 years ago
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C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")")
In news: timestamped Tue, 06 Mar 2007 16:20:27 +0000, MartThat sounds like one for the .sig file!" Thank you, I aim to please! Prof. Giovanni De Micheli said on April 2nd, 2007 while lecturing: "I...
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17 years ago
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Why I cannot use the XAUI core(generated by xilinx)
I use COREGEN to generate XAUI(choose device Virtex5 110t), but I cannot do simulation with modelsim6.1f. It is always reporting the following error. I think maybe there is something in modelsim...
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17 years ago
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is there any opensource alternatives to platformstudio and microblaze development?
is there any opensource alternatives to platformstudio and microblaze development?
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17 years ago
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File open, read and write in Xilinx EDK 7.1
Hi, Iam writng a c code in Xilinx EDK 7.1 and am having problems with the fopen construct. Iam trying to read data from a text file, process it and then write it back. I read the documentation and...
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17 years ago
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record type port in vhdl and simulation in ISE
Hello, I have an entity in VHDL that one of its ports is a record type. I am trying to create a test bench wave form to test the code but when ISE creating a test bench; it doesn't create the wave...
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17 years ago
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Modelsim Low and High violations
When simulating a post-routed design in ModelSim, I get a number of setup, hold, recovery violations such as: # ** Warning: /X_FF SETUP Low VIOLATION ON CE WITH RESPECT TO CLK; Can somebody explain...
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17 years ago
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Word sync in Cypress FX2 fifos /w 8 bit bus
Any Cypress FX2 (USB) gurus out there? I have one of these devices on an FPGA board (Digilent Nexys), which only provides an 8-bit external datapath instead of 16 bits. I'd like to stream...
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17 years ago
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MGT Clocking
I am currently trying to free-up some DCMs for use in other parts of our design, so I am trying to make some MGTs share DCM outputs. Currently I have one DCM per each of the eight MGTs which uses all...
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17 years ago
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