Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How do I constrain Xilinx to implement multi-cycle paths?
Due to RAM access, I calculate data on rising edge while feed into the RAM on negedge edge of clk_100m_i, which is 100MHz. To me, the delay between my_data and latching into ram_data is 15ns, while...
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17 years ago
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PLB Master to communicate with the BRAM
Hi, I need to make an IPIF PLB MASTER and I have some question about this purpose, -what is the IP2IP_Addr bus ? -why the burst mode (even if is not selected) is automaticaly created with the IPIF...
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17 years ago
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No login in uClinux (Petalinux)
Is there some method to avoid "login prompt"?. The reason is that I have designed an application over uClinux and I want that this app run without introducing any information. Could I edit some...
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17 years ago
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Are there Quartus II Web Edition limitations?
Hello! I have a simple question: Are there any limitations to the Quartus II software when I use a web edition liscence? (v 7.0) I ask because I am not able to find the correct configuration...
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17 years ago
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Back annotating to RTL
Tracing timing violations in the post-p&r generated netlist can be cumbersome with all signal merging/renaming and inserted buffer. I was wondering if there is a way that I can back annotate the post...
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17 years ago
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spartan 3e availability
If spartan 3e are really in mass production, why is it, that this kits: DO-SP3E1600E-DK-UNI-G are never available ? Not from xilinx (where the online store is just joke to navigate, sending peaple in...
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17 years ago
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SETUP & HOLD time confusion
In the Xilinx Synthesis and Simulation Design Guide there is this phrase: "While Xilinx data sheets report that there are zero hold times on the internal registers and I/O registers with the default...
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17 years ago
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XPS behavioral simulation fails: the design is not loaded
After designing a peripheral and checking that it is working with the BFM simulation, I am trying to simulate the whole system. I created a simple system with BSB in order to get experience with this...
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17 years ago
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Problem with EDK 8.2 MicroBlaze Tutorial
I am trying to work through the "EDK 8.2 MicroBlaze Tutorial in Spartin 3" When I get to the point of "Generate Programming File" to implement the design on page 26, It appears that ISE does not call...
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17 years ago
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Changing LUT input size in synthesize
Dear all, I'm doing research on FPGA's LUT input size. And i'm using synplify pro to synthesize vhdl/verilog to edf for virtex2 device. Do you know how to limit the LUT input size to 1, 2,3 in...
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17 years ago
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EDK + XMD
Hi, Here is my problem. My memory map is as follows: ISBRAM : 0xFFFFE000:0xFFFFFFFF SDRAM : = 0xF0000000:0xF1FFFFFF I download bootloop program with the bitstream. The program I want to execute is...
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17 years ago
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how two sine signals are multiplied in VHDL language
hi all, iam doing projevt on Digital down that i need to multiply RF signal and LO signal . which type of multiplier is suited for multiplication of two sinusoidal signal using FPGA.if any body is...
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17 years ago
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Which are the best books about CORDIC algorithms and applications
Hi, I want to buy two books on CORDIC. One is focused on CORDIC theory and algorithms, another on CORDIC applications. Which is the best book about CORDIC algorithms? Which is the best book about...
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17 years ago
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XST and Verilog $readmemh
In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion. I look at the .syr output file from XST, and it claims to have read the file. But......
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17 years ago
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Timing violations though constraints have been met
I keep on getting Setup time violations from ModelSim despite the fact that my design successfully placed and routed within the given time constraint. Can anybody suggest a reason for that or a work...
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17 years ago
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