Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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OPB To Wishbone Bridge
Hi all, I am looking for an OPB to wishbone bridge to let OPB talk to my IP via wishbone in EDK. I have read some posts on OPB-> wishbone wrapper (available at Had a look at the wrapper, which raises...
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17 years ago
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combinatorial vs sequential
hi could you please explain wht is to be coded in combinatorial and wht to be coded in sequential. am bit confused Thanks and Regards lokesh
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17 years ago
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Running Xilinx 9.1 GUIs on FC6
I've been trying to launch ISE (9.1SP3) and I get this error FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - The executable can't be found. The installation was not complete. Process will...
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17 years ago
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FPGA High speed Transceivers for source synchronus bus application
I would like to know if you have used the High speed FPGA Tranceivers for source synchronous bus application. In my application, I have 20 bit outgoing and 20 bit incoming bus. Is it possible to do...
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17 years ago
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Writing to BRAM using OPB
Hi all, I am trying to make a peripheral attached to the OPB bus. This peripheral has a BRAM block in it. The idea is to check how to read and write to the simple BRAM block and later add some logic...
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17 years ago
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Why 166Mhz DDR?
Hi, I was wondering how the number 166Mhz for DDR came up? Why not say... 200MHz/250MHz DDR? I am sure there is some thought process behind that, could someone help me walk through? Thanks in advance...
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17 years ago
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[xilinx] par [placer] consistency
Hi! I have a [MCU] core running at 50MHz which I use for generating patterns/reading status of some other logic, mapped on the same fpga (spartan3). I have noticed the timing after placement/routing...
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17 years ago
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Pin Count requirements with MICO32
Hallo, has anybody some pin count requirements for the Latticemico32? I know, it depends heavily on the choosen combination, so information to the configuration is welcome. CLB Requirements would also...
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17 years ago
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How many RAM words can I implement in my Xilinx FPGA?
I would like to make a dual-port RAM inside my FPGA... I am using a Spartan 3 1000K gate model... I know it takes a pretty good number of macrocells to do this but I don't quite know enough on the low...
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17 years ago
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ML506 Platform Flash
Hello Has anyone figured out how to program and configure from the Platform Flash on the ML506. I have spent a lot of quality time with the ML505/ML506 Getting Started Tutorial (ug348.pdf) without...
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17 years ago
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picoblaze C compiler download wanted
I was hoping to download Francesco Poderico's Picoblaze C compiler today, but unfortunately his domain is expired. Google didn't turn up any other sites from which I can download it; does anyone know...
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17 years ago
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SoC
Hi experts, I want to persue my PhD in SoC , would you tell me best institutes or research goroups in Europe in this area. Thanks, Baig
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17 years ago
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Order of the synchronous operations
Consider the very simple VHDL code at the end of the message. For each clock cycle two operations are done: 1) A counter is incremented; 2) The bit 0 of the counter is checked. If it's '0', an output...
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17 years ago
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Simulating LogicCores with Webpack
Is it possible to simulate logic cores with WebPack? I'm using Webpack 9.1.03i. First I tried the ISE Simulator, then the free ModelSIM XE/III Starter, and failed with both. OTOH, I'm not sure that I...
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17 years ago
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JTAG ID code 0xFFFFFFFF
Hi, I need some help with my Altera Dev Kit (STRATIX DSP S80 Development Board Rev 1.2). I no longer seem to be able to program my device. It was working properly until I started getting the following...
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17 years ago
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