Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
No Synplify evaluation?
Good afternoon.. Has anyone being lucky in the past getting a Synplify for Linux evaluation license? Mentor has some online feedback form to request an evaluation license, but apparently their eimail...
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xilinx unused I/O state
Hi, What is the default state of the unused I/O pins for Xilinx FPGA (Spartan 3E)? For Altera FPGA, it can be set as input tri-stated or as output driving gnd, etc. Is there any counterpart operation...
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define variable in ISE9.1 Tcl scripts
Hi, I've a question about ISE9.1 Tcl scripts. Is it possible to include `define in Tcl project scripts to determine module to synthesize according to `ifdef... `endif placed in the verilog sources ?...
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plb_tft_cntlr_ref for an ML405 EDK Project
Dear all, I am working with an ML405 and trying to put together a project of my own that uses the plb_tft_cntlr_ref IP from the example project. I tried to import the IP using the "Create or Import...
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Interfacing FPGA with TTL
Hi, I am using the UP2 development board from Altera. I have programmed a simple ALU in it. I have done some hardware tests on it through its expansion slots but the results are inconsistent. To...
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type/subtype definition in entity
I want to define a type related to entity generics, like an array in the following codes. But It seems I have no places to put those subtype/type statements in the entity. I can not use package to...
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Debug monitor for Freescale MPC5200
I have put a debug monitor for the MPC5200 PPC processor for download (free for development purposes) at . Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic...
 
License Key based on WLAN/Bluetooth MAC
Evnin' To make life easier when I decide to abandon an old Workstation to get a more powerful one... Can for example Quartus or ispLever use the MAC address of a Bluetooth or WLAN dongle so when I buy...
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Matlab Simulink HDL coder generated code interface.
Hello, I read about Matlab/Simulink HDL code and did simple test with it. I couldn't understand what the meaning of ports to the generated code is and I couldn't find any sample timing for them. Is...
 
Safety of bidirectional lines
Hi, I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. The bus of the NET2272 is similar to that of a parallel RAM, with address lines, bidirectional data bus, and read/write strobe...
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Embedding Altera SignalTap II on 1st synthesis/implementation pass
Hi, I am currently working with a large design with long synthesis and implementation times. The design is synthesized with Precision RTL and the gate-level netlist is exported manually to Quartus II...
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dual port memory from single port RAM.
Hi all, My ASIC design requires dual port memories(one port R/W other port only read) but there is a constraint on using it. Instead I am planning to create this memory using single port RAM's. Writes...
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Xilinx ISE 9.1
It seems to work better (much better than 8.1), but seems to have a few issues that make it a bit hard to use. 1/ Sometimes it auto trims logic which is required - particularly when it is associated...
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PLB Master
Hi, I build a IPIF master with Create/Import Peripheral. I try the example write in the user_logic.vhd: -- Here's an example procedure in your software application to initiate a 4-byte -- write...
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vpw/pwm controller
hi all, can anyone tell me where i can get a free vpw/pwm controller either in vhdl or verilog according to j1850 standards. thanks , asha.
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