Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Free Hardware
This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs.
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16 years ago
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xilprofile for edk 8.2
Hi All, After searching the web (and xilinx's own site) for any references to the "xilprofile" library or documentation and only finding XAPP545 which is for the ppc and edk 6.x. I was wondering if...
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16 years ago
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Question about reset signal for several DCMs in EDK design.
Hello, I have several DCMs in my design and they are phase synchronized. I generated them respectively in the DLL mode from the system clock. The simulation is fine. But when I put the design on...
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16 years ago
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Spartan 3 IOSTANDARD vs VCCO
An output pin voltage swing is determined by VCCO, so how else does specifying LVCMOS25 vs LVCMOS18 as the IOSTANDARD affect output signals? Thanks
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16 years ago
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Regarding drivers for FPGA based PCI cards
Lately I've seen a couple of posts that ask for a PCI based prototype boards which has drivers available. Well actually, almost any post which asks about PCI based prototype boards asks for drivers as...
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16 years ago
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Summer with fpgas
Hi, I'm a beginner in the fpga world.I've been reading up some of the books listed in this group in other posts, and doing basic designs (like contollers, ALUs etc). Although the books and my school...
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16 years ago
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Altera MPM7064LC84 vs EPM7064LC84
Can anyone explain to me what the difference is between MPM7064LC84 and EPM7064LC84? Thanks, Derek
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16 years ago
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Re: 64 bit matrix multplication
Asking this on a VHDL newsgroup may not be the best idea... try (given that you are thinking of using Xilinx devices) - I'll cross post this there... Yes. There are many more questions to be answered...
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16 years ago
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Ask: why xilinx FPGA pin assignment couldn't pass p&r?
Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The following pin assignment constraints were specified in .ucf for Xilinx XC2V8000...
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16 years ago
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Altera M4K memory usage
Hi everybody, I'm using a Cyclone II EP2C20 which has 52 M4K memory blocks with each 4096+512bits. I want to use the whole memory, but I can't use the additional 512bits of the M4K blocks. if I make...
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16 years ago
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Question about Xilinx ISE (problem with signals trimming)
Ive got a problem like mentioned, During "map" signals that are used in the design are being trimmed and than I get errors that these signals are missing. Anybody knows how to prevent ISE from...
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17 years ago
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VHDL source code for polyphase filter
Hello, Where can I find the VHDL ( or verilog) source code for polyphase filter? Is there any free implementation around? Regards
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17 years ago
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Any recommendation for proto PCB
Hi everybody, Currently I use for my standard PCB prototypes. They are cheap and rather good but they have probably too much work these days and I had unexpected delays on several boards. So I'm...
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17 years ago
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Problems in simulation (Webpack 9.1.03i)
Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear in the transcript window: Running Fuse ... WARNING:HDLParsers:3583 - File...
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17 years ago
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IOB and DIFFM/DIFFS
Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The following pin assignment constraints were specified in .ucf for Xilinx XC2V8000...
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17 years ago
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