Latest threads in Field-Programmable Gate Arraysshow only best voted threads
Subject | Author | Posted | Replies | |
---|---|---|---|---|
|
How many Xilinx devkits does one need?
Hi I do have have plenty of Xilinx development hardware. I did thinkt hat for sure enough that i can pick up some board for almost any task. Now I just wanted to check out the Xilinx standard...
2
|
16 years ago
|
2 | |
|
TigerSHARC TS201 to PLX 9656
Hi, Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 device? I'm trying to implement this in a current project and need details. The bridging is done via an Altera FPGA which also has...
5
|
16 years ago
|
5 | |
|
Is there a reset signal available in verilog in Xilinx FPGAs?
As a sample here is some code. To be clear: I am not looking for alternate ways to code the following always block; I would like to know a way to access the power on reset from verilog. The block is...
2
|
16 years ago
|
2 | |
|
Placement error for adjacent pins
I have two pin one is IN and the other is INOUT and they each one goes to the D input of two FFs clocked by two different clocks Clk1, Clk2. When I start the PAR process, Xilinx tool complains with...
4
|
16 years ago
|
4 | |
|
Killed a Stratix-II Nios II Altera devkit, How to repair?
Hello, to due a unfortunate chain of events, the cooler of the ep2s60 dropped to the right side of the chip and short-circuit an unkown number of lines (could be at least 1.2V and GND). Fuse F3 has...
3
|
16 years ago
|
3 | |
|
constraints for design-generated clock
Hi, I am designing a memory controller for a Micron CellularRam and would like to ask what is the best way to generate and what are the optimal buffers, constraints for the clock that needs to be fed...
—
|
16 years ago
|
— | |
|
Problem cascading 2 DCMs
Hi everyone, I have a problem that is bugging me for 2 days now and I was hoping someone here might be able to help me out. The problem is as follows: I want to implement a DDR2 RAM Controller in a...
21
|
16 years ago
|
21 | |
|
chip to chip high speed interconnet bus
Hi,everyone,now i want to know how can i change the high speed data between 2 chips=A3=A8one from lattice scm and one from xilinx=A3=A9,now I u= se the lattice sc for pci-e interface and the xilinx...
—
|
16 years ago
|
— | |
|
a question about DDFS
Hi, I am implementing a direct digital frequency synthesizer in FPGA. It follows the equation Fo = N * Fs / (2^M) The implementastion is done by an M-bit phase accumulator. My question is: if 2^M...
2
|
16 years ago
|
2 | |
|
Prope timing constraint for this pin?
Hi. I'm working on a V4 project, but I struggle with the timing constraints. The design has one 125MHz oscillator. In an EDK submodule, this clock is divided to 62.5MHz for the bus clock (system...
—
|
16 years ago
|
— | |
|
one extra slipway board from fccm
Hey all, I still have one more slipway board left over to give away; email me if you want it and I'll mail it to you. If you don't know what I'm talking about, this might help: Please don't laugh at...
3
|
16 years ago
|
3 | |
|
N00b question about DCM
I have a Spartan3E Starter Kit, and I am trying to figure out how to use the DCM to double the freq from 50MHz to 100MHz. I wrote a small verilog program to blink LEDs 0-3 based on the 50MHz clock,...
2
|
16 years ago
|
2 | |
|
Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
2
|
16 years ago
|
2 | |
|
Quartus Fitter Seed Setting
Hello, can anyone comment on setting the "Seed" value in the Fitter group under Setting? How does increasing the value produce a better fit? thanks, joe
2
|
16 years ago
|
2 | |
|
memory interface for DDR/DDR2 with xilinx spartan 3E/3A starter kits
Hi groups, Hi Xilinx folks, For edu., I am doing some test with DRAM access with xilinx starter kit (3E/3A). I use xilinx mig 1.7 tool and I found some reference design in E. Crabill s3ak_test But it...
—
|
16 years ago
|
— |