Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
I'm a student in year one, and this is my first, more serious project, so bear with me. I've completed the schematics, and the timing simulations work fine too. Now, as the next step i would like to...
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16 years ago
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My Dear Spartan-3A, Please Please WAKE UP!
After giving up the search for Xilinx supplied MicroBlaze reference designs for Xilinx Spartan-3A kit, I made the reference design using BSB in EDK 9.1SP1. No problem encountered until the attempt to...
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16 years ago
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Xilinx 9.x SW == Total Frustration (so far..)
Its really hard to see how some software manages to get worse and worse every major release! Installed - ISE 9.1+SP3, EKD 9.1+SP1 Applied hotfix for EDK as described in AR24143 This is LATEST RELEASE,...
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16 years ago
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Area constraint - trust Low Level Synthesis?
My FPGA is getting a bit crowded. I have a huge distributed FIR in my Spartan3/400. When synthesising the design I get conflicting (?) area constraint messages from Low Level Synthesis and Final...
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16 years ago
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prevent ROM inferration
I have a state machine design with big case statments (VHDL). When I compile with Precision RTL it infers block ROM, which exceeds the actual number of EBR blocks in my FPGA. I am using a Lattice...
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16 years ago
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Unused Pin setting on per-pin basis
Hi all, I've got a custom FPGA board with a number of peripherals connected to the FPGA. I need to keep the connections between the FPGA and unused peripherals in a sensible state. Is there a way I...
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16 years ago
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How to Black Box my IP using Quartus II
I want to black-box a sub-module in my design (written in VHDL) that is targeted for a Altera's Cyclone II FPGA. I have tried the VQM netlist writer inside Quartus to create a device netlist that can...
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16 years ago
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DCIRESET in Virtex-4
Hi everybody, My question concerns DCI and temperature. If the temperature of the chip changes considarably between the end of the init process and the normal functionning, is it a good idea to...
1
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16 years ago
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Xilinx tools concern
Starting a new design using both V2P and V5. I see with concern that the latest Xilinx tools might have issues. We need to upgrade as the candidate development machine is running 6.2-something (don't...
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16 years ago
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Read 64-bit value over PLB
Hi, My question is straight'n'simple: what's the *most efficient* way of reading a 64-bit value from a slave PLB peripheral in software? Is there any *weird* behaviour I should be made aware of when I...
3
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16 years ago
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ISE 8.2 Strange cache problem? Warning...
I am working on a little project using the 8.203i tools. P&R is taking quite a long time now. Was in the middle of a build and realized I had forgot something. Selected STOP in the Implement menu and...
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16 years ago
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Where can I find the pass transistor's working curve under 1.2V?
Hi, Please help. Where can I find the pass transistor's working curve under 1.2V that is widely used in IC design preferebly in any articles, instead of in books? Thank you. Weng
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16 years ago
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About ModelSim
Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I wrote the codes here but it doesn't work. Any suggestions about this is very...
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16 years ago
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Open source Programmer, Logic Analyzer and In-Circuit Emulator Project
Guys, I saw this on Slashdot and thought of CAF. The PLAICE is an open source hardware and software project developing a powerful in-circuit development tool that combines in one device the features...
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16 years ago
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synthesis tools
Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I am thinking of tools from Synopsys, Mentor graphics and synplicity. If there are...
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16 years ago
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