Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FPGA board for video processing
Hi, I am looking for a new powerful FPGA board for video processing algorithm development. My work will focue on the architecture design of video signal processing algorithms. I hope the other parts...
4
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16 years ago
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Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
Hi, My name is Bryan from Xilinx Asia Pacific. I have on hand a Spartan 3A Starter Kit . However, I was trying out Multiboot Demo Config option 4 which is a video pass through demo that does not seem...
8
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16 years ago
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8 | |
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Atom HDL
Hello, Atom is a new high-level hardware description language embedded in the functional language Haskell. Atom compiles circuit descriptions in conditional term rewriting systems down to Verilog and...
13
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16 years ago
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13 | |
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JTAG Loader tools won't execute
I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The system cannot execute the specified program" message in the...
5
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16 years ago
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lwIP RAW mode support for V4 temac
Hello, Does anyone know of an example using lwIP in RAW mode with the Virtex-4 temac? From what I understand, the lwIP temac port seemingly only supports lwIP in sockets mode with xilkernel. I don't...
11
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16 years ago
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11 | |
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Tcl slash backslash
Hello all, I'm using XP and paths are separated with backslashes. But Tcl uses slashes. How do you handle that, are there any tricks? I'm working mostly with ISE 9.1, but looking for a common...
2
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16 years ago
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2 | |
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Prunnning Register missunderstood!!
Hi everybody, After synthesizing my architecture using Synplify pro, i received several same warning like: ... hdlFSM_Write.vhd":65:7:65:8|Pruning Register ...... what does it mean Pruning register? i...
2
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16 years ago
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2 | |
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Select pullup, pulldown or none via embedded S/W
Hi, Within our ASIC library, we have an I/O pad which has input pins allowing us to select whether a pullup, pulldown or none is enabled for this pad. This is very useful for GPIO. We are using an...
23
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16 years ago
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23 | |
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Use of "blocks" in Quartus design
I'm a fairly experienced user of Quartus but I've never considered using "blocks" in block design files i.e. my design hierarchy consists of only symbols with a mixture of Verilog and graphic design...
4
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16 years ago
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4 | |
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Wait-for / until won't work ? Xilinx Spartan 3
Hello. I'm new to FPGA desing, so could you please help me with this little = problem. To run my sensor I must have some delays in communication with it = (DS18B20). When I put this into my code "wait...
25
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16 years ago
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25 | |
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PLB master with burst mode
Hi, I build a PLB Master in single byte transfer mode and it works well. Now, I try to use the burst mode and I don't understand something. For a burst transaction, at each rising edge of the clk, a...
3
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16 years ago
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First MicroBlaze demo design for Spartan-3A Starterkit
Hi Xilinx hasnt provided ANY MicroBlaze demos for the new Spartan-3A Starterkit so others have to fill the gap, and I am trying to make a start, here is very simple EDK system that is tested to work...
7
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16 years ago
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Video scaler for Spartan 3E?
Hi Just want to do a feasibility study on whether it is possible to design and implement a video scaler on a Spartan 3E? Well my tutor kind of came up with this proposal for a project of mine but then...
20
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16 years ago
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Xilinx WebPACK 91i on vmware RHEL4
I am trying to install the Xilinx ISE WebPACK software on a vmware virtual machine running RHEL4-WS. I made the machine and installed RHEL from scratch (it works that far) an now I'm trying to install...
1
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16 years ago
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OPB Master Peripheral
Hello all, I am working on a project, in which am trying to make OV7660 camera protoboard to talk to ML300 Xilinx FPGA board.I have a general question regarding OPB bus. Here is the set up: I am...
3
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16 years ago
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