Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Uart problem, xapp223 + Spartan3A
I'm using Ken Chapman's uart_tx in a Spartan3A design. The HDL compler can't find the module/primitive, so I wonder if I did everything right here. What I did was the following: - Download and unpack...
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16 years ago
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xc3sprog and spartan 3e/3a
Hi! I was successful in the past using xc3sprog to program Spartan3 (50, 200) and the associated serial flash. Can anyone say something about xc3sprog and Spartan3E and Spartan3A devices? A quick scan...
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16 years ago
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NgdBuild:604 error
Hi all, I'm implementing a design which uses ROMs. The design was synthesized under precision. I used the .edf file for implementation under ise 9.1.03i. Unfortunately, I'm getting this error:...
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16 years ago
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V5 serial link
I have been tetsing with Xilinx V5 LXT board for transceiver evaluation. Currently I am focusing on the transmitter to determine channel alignment. This particular board has 16 transceivers. We...
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16 years ago
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JTAG_SIM_VIRTEX5
Guys I am trying to simulate the BSCAN_VIRTEX5 component. The Xilinx simulation guide, sim.pdf, says that you can instantiate a JTAG_SIM_VIRTEX5 in your testbench to control the BSCAN component. So...
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16 years ago
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ISE9.1: ERROR:Place:911
When i add these 2 constraint to my UCF file: CONFIG POST_CRC = "ENABLE"; CONFIG POST_CRC_SIGNAL = "FRAME_ECC_ONLY"; I get these error messages while doing the timing driven packing phase in the map...
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16 years ago
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Accessing SRAM on the Spartan-3 Starter Board
Dear All, I'm sure this question was already been posted (and answered) in this list, but I could not find a suitable answer for my little knowledge of this matters, so, with my apologies, i'm posting...
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16 years ago
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Altera enters as second the low-cost multigigabit tranceiver FPGA scene!!
Hi After Lattice ECP2M now also Altera has announced low cost FPGA family with high speed Serdes ! Antti
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16 years ago
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Craignell - Spartan-3E DIL Module
We have now posted schematics for the 40 pin variant of Craignell on our engineering website for those interested in more details. It's here John Adair Enterpoint Ld.
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16 years ago
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Gain and Offset Correction
Hallo, do you know a way to perform gain and offset correction of the adc output in vhdl? Many Thanks Marco T.
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16 years ago
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Darnaw1 - PGA Spartan-3E Module
We have just posted the schematics to this product and given some more details on I/O counts on our engineering website. Details are here I am still interested in feedback on this product as we start...
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16 years ago
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DVI over fiber
hello I need to design DVI over FIBER my idea to do as follow DVI to data then to FPGA the FPGA will use memory sunc SDRAM or DDRAM will send info via phy and the same on RX side I need help with FPGA...
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16 years ago
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ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!
Hi, everyone I've been stuck on this problem for a couple of days, and still couldnt figure out how this happen. I have an XPS/ISE combined project. The part of ISE project is a hardware accelerator...
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16 years ago
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How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
I'm restricted to 30Mhz LVDS clock input. From this, I need to generate 240Mhz to be used internally. Restriction comes an ASIC that I'm interfacing to. What options do I have here? Based on what I...
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16 years ago
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ISE 9.1 Hierarchy Problem
I recently switched over to ISE 9.1 and I noticed a problem where ISE won't recognize the design hierarchy. Thinking that it might be something specific to my design, I tried the example design files...
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16 years ago
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