Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Lockup with Xilinx mch_opb_ddr
Hi, I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze design. Beside the Microblaze, another bus master is accessing the DDR. Since I need to avoid some deadlocks over the...
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16 years ago
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does SRL exist in non-xilinx FPGAs?
Hey, Is there any non-xilinx FPGA that has the equivalent of Xilinx Virtex SRL component as a basic component logic? If Not, why? has Xilinx patented it? Many Thanks :)
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16 years ago
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Anyone using the TimingAnalyzer
Hello All, Back in the 2002, I was developing a program called the TimingAnalyzer. Below is a copy of an announcement made on this forum back then. I was wondering if anyone has been using it since...
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16 years ago
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Camera Control
Hello, I have a xupv2p board and I am wanting to use this board to perform image processing from 2 camera-link based cameras. I am building a connection board that will connect the cameras to the...
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16 years ago
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Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
As subject: all system are go and green on the Spartan-3A Starterkit board. No issues. Just working :) Antti Lukats PS demo download also available now from our site.
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16 years ago
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How to Ask a Question
Hi - In light of a recent flameboree in these parts, I thought it might be helpful to provide a link to an article entitled, "How to Ask a Question the Smart Way." Although aimed at programmers and...
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16 years ago
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Digital gain and offset correction
Hallo, which is the way to perform digital vgain and offset correction using a fpga? Thanks, Marco T.
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16 years ago
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Xilinx Webpack 9.1i.03 Verilog synthesis bug?
For the combinational-logic of my state-machine, if I use an always @*, Xilinx XST erroneously optimizes/removes the logic, and then rips out any downstream load-logic. reg [6:0] s_instr_category; //...
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16 years ago
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downto usage in EDK
Hi, I vaguely seem to remember a provision on the use of downto in EDK. I tried to dig this out before posting this with no luck---Can't remember where I came across this though I tried a couple of...
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16 years ago
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plb_tft_cntlr_ref in XUP
hi everybody, I'm using plb_tft_cntlr_ref IP in EDK8.1 project, based on XUP Vertex2Pro Development Board, now having some troubles. I have created a project and added the plb_tft_cntlr_ref to it...
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16 years ago
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PowerPC_GPIO
Has anyone measured the cycles needed for a PowerPC to output data in a GPIO port? I am using a Virtex-II Pro device and plb_GPIO peripheral, and I measure ~100 cycles.
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16 years ago
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PowerPC_DDR
I am trying to interface a PowerPC in a Virtex-II Pro device with an external DDR memory on the board. I am using the following fucntions to read an write to the memory: //write num. 300 to position 0...
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16 years ago
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Power Consumption Estimation for PCI card, any advice?
Hi, everybody I am designing a PCI video capture card. The main ICs are: Cyclone I (EP2C35F672c6), ADV7181, ADV7123, PCI9054, 128M SDRAM etc. Now I am makin a power consumption estimation for this...
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16 years ago
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how to choose the perfect fpga support
hi every body, i want to implement a vhdl program into an fpga support ( the program is compressing video ), i want know what are the basics that i should know to choose the perfect fpga( for example...
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16 years ago
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V4FX PPC ICU data transfer timeout?
Hi. Debugging a board with V4FX12 I noticed a strange behaviour of the PPC ICU. It seems that the ICU has an undocumented data transfer timeout. According to the docs, the PLB arbiter implements a...
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16 years ago
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