Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Power Consumption near Timing Failure Point
I know that an FPGA's power consumption is basically linear with clock frequency, but does anybody know what happens when the maximum clock frequency for the design is approached? Does power...
12
|
16 years ago
|
12 | |
|
|
Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
Hello, I am graduate student in the Dept. of Computer Sc. & Engg. in USF. We are using a Digilent XUP2vpPro board for one of our research projects. I am trying to interface a Kingston 512 MB DDR RAM...
7
|
16 years ago
|
7 | |
|
|
Designer
Good evening guys and gals, my name is Mark and I am a technical recruiter in Mclean, VA. I am sorry to bother all of you, but I have one quick question and I hope that someone might be able to point...
2
|
16 years ago
|
2 | |
|
|
LF VHDL to FSM bubble diagram translator
Hi all, I was wondering if there is such a thing available? I found a few free and commercial tools to edit/create bubble diagrams, which would then generate VHDL code, but I would like to be able to...
3
|
16 years ago
|
3 | |
|
|
ise project navigator can't dereference edk pcores from XilinxProcessorIPLib
First of all. Thanks for the bus macro advise. The second problem still remains. After creating a system with base system builder wizard from EDK's XPS and generating its netlist(s), I wanted to join...
4
|
16 years ago
|
4 | |
|
|
Using dynamic reconfiguration ports of DCMs on Virtex 4
Hello, I've been reading the posts in this forum for a long time. This is my first time asking a question here. I'm working on possible dynamic reconfiguration of DCMs to change the PHASE_SHIFT on the...
—
|
16 years ago
|
— | |
|
|
Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory
Hello, I've some problems with reading from my sd-ram. On my FPGA is a Xilinx Virtex 2 XC2V1000 chip and I want to use the ram for greater software- applications. The first problem was, that the fpga...
3
|
16 years ago
|
3 | |
|
|
debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL
good thing do not seem to be long online, the bitstream decompiler project seems not available, at least I can find the relevant weblinks any more, maybe there is new hidden URL? the last one used to...
—
|
16 years ago
|
— | |
|
|
How low DDR2 Clock Frequency can be? To make it work on FPGA.
Hello, I have a DDR2 Controller ASIC rtl, which i need to put on FPGA and validate it. The problem is, i am not able to get this controller run on more than 50-60 Mhz on Virtex4 FPGA. Now, as everyone...
14
|
16 years ago
|
14 | |
|
|
Xilinx ISE 9.1 Simulator does not work with glibc 2.5
Hi List, I cannot run the ISE-Simulator on a Gentoo Laptop with glibc 2.5. The simulation seems to run fine, but the Simulation window is not showing up. I've found that recently someone else had...
2
|
16 years ago
|
2 | |
|
|
coregen -> simulation error in modelsim
When i try to simulate a coregen generated single port ram, i get a error from modelsim : # -- Loading package blkmemsp_pkg_v6_2 # -- Loading entity blkmemsp_v6_2 # ** Error: ram.vhd(112): Internal...
3
|
16 years ago
|
3 | |
|
|
Xilinx EDK: Slow OPB write speeds
Hi All, I've a simple peripheral with an OPB interface. In a nutshell I've been getting some very slow write speeds over the OPB and wanted to see if this was normal, or if there was anything I can do...
10
|
16 years ago
|
10 | |
|
|
reading IDCODE from parallel bus?
Is there any way to read IDCODE (and execute other jtag commands) using the parallel config bus? I can't find any information on this, mostly because of polluted results. Thanks
2
|
16 years ago
|
2 | |
|
|
bus macros for partial reconfiguration of virtex2pro?
Hi everybody. I'm sitting over a partial reconfiguration project for university. I'm absolutelly new to this topic, but as an introduction to this topic, of course I 've already read the concerning...
1
|
16 years ago
|
1 | |
|
|
Timing constraint question
Hello, I am trying to specify a timing constraint for a latch that I have in my design. I need to make sure that from the rising edge of the clock to when a control signal goes high that causes the...
8
|
16 years ago
|
8 |