Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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can JTAG port of CPLD gets damaged?
i am using altera quartus 2 tool to programme it through byte blaster cable. I have installed drivers for the connections intact. i am getting error as "Unable to scan device." My assusmption was may...
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16 years ago
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too brief documentation?
Currently using this board. however I kind of feel that the documentation in using the board is abit too brief For example, I do not know how to set the clock frequency based on the PLL set switches....
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16 years ago
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Avnet Virtex-4 LX25 Evaluation Kit
Hello, Is thery anyone who has worked with Avnet Virtex-4 LX25 evaluation board. I am trying to communicate with the board through the provide USB interface in the form of Cypress USB Fx2 chip. The...
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16 years ago
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Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
Hello, I have recently bought a Virtex-4 LX25 evaluation board from Avnet. It has Cypress FX2 chip for USB 2.0 communication support. The generic USB driver provided by Cypress is of no use to me....
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16 years ago
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Cyclone II can't enter in configuration mode with EPCS1.
HI everybody, I am trying to configure a cyclone II with EPCS1 boot loader. the EPCS1 program perfectly with quartus and byteblaster II cable. But when at the nstatus pin on the FPGA, it's like it's...
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16 years ago
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Cyclone II can't enter configuration mode with EPCS1 active serial.
Hi I would like to ask you guys about a cyclone II power-up problems. I read all datasheets from altera concerning all the steps to enter finally in USER mode with the FPGA properly configured. I have...
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16 years ago
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seeking insights for potential reconfigurable computing application platforms
I am currently working on a NASA program focused on the development of Radiation-Hardened Electronics for Space Environments (RHESE). One portion of the sub-project I am working in support of is aimed...
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16 years ago
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Mutiple MAC on OPB Bus
Hi, Is there any constraint regarding the number of Ethernet MAC that you can place on the OPB Bus? I have attempting to put 2 MACs on the Bus, but as soon as a instantiate the second MAC and attempt...
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16 years ago
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CML output swing for V5
As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential voltage from the Xilinx FPGA? Test01
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16 years ago
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NIOS2 GNU tools under Windows Vista
Anyone have tried to run NIOS2 tools chain (especially gcc) under Windows Vista ? If I try I get the "fork_copy" error on some "C" modules. Any idea ? Best regards /Alessandro
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16 years ago
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Unable to scan JTAG chain
I am using max 7000s series cpld.i am using altera byte blaster cable. i am getting error as "unable to scan device chain .cann't scan jtag chain". what is meaning of this error? what i need to do,to...
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16 years ago
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how to delay a signal in virtex FPGA
Hi all, I've to delay a signal without using clock. So I want to use propagation time across logic functions like AND but, when I will synthetize my design, ISE will symplify and remove all my AND...
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16 years ago
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clock wide pulse transfer b/w clock domains
Hi, Please suggest me how to transfer a single clockwide pulse from high frequency clock domain and create a single clockwide pulse in a slow clock domain? What are different methods available? Thanks...
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16 years ago
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Global ressource problem
Hi i'm developping an architecture using Libero and Actel FPGA, i had a problem with global ressources, i had 8 global ressources and the FPGA contains only 6, is there any way to oblige the compiler...
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16 years ago
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SERDES question (Lattice ispHSI)
Hi! I need to design a simple serializer/deserializer as part of my bigger experimental project. I've started with reading various application notes from Lattice, Xilinx and Altera, as I don't feel...
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16 years ago
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